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Brief Introduction of High-Speed Circuits for Optical Communication Systems. Zheng Wang Instructor: Dr. Liu. Outline. Introduction System Overview TIA design Limiter Design Frequency Acquisition CDR Design Prospects.
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Brief Introduction of High-Speed Circuits for Optical Communication Systems Zheng Wang Instructor: Dr. Liu
Outline • Introduction • System Overview • TIA design • Limiter Design • Frequency Acquisition • CDR Design • Prospects
Global Internet Backbone Growth(data released by research firm TeleGeography in 2002)
SerDes Transceivers(high–speed, full–duplex, serializer/deserializer)
Dedicated line broadband speeds • T-1 - 1.544 megabits per second (24 DS0 lines) Ave. cost $1,200./mo. • T-3 - 43.232 megabits per second (28 T1s) Ave. cost $28,000./mo. • OC-3 - 155 megabits per second (100 T1s) Ave. cost $49,000./mo. • OC-48 - 2.5 gigabits per seconds (4 OC12s) no est. price available • OC-192 - 9.6 gigabits per second (4 OC48s) no est. price available
TIA (Transimpedance Amplifier ) • Transimpedance Gain • Bandwidth & Power Dissipation • Voltage Headroom • Input & Output Impedance
TIA Circuit (a) • Gain = ? • Noise contributed by M1 rises at high frequency • Poor performance at low voltage supply
TIA Circuit (b) • Gain = RF • Value of RF can be maximized because it does not limit the voltage headroom
TIA Building Block • Intel LXT16865. Power Supply 3.3V. Power dissipation less than 160mW • high optical input sensitivity (as good as -20dBm). Suitable for long-haul transmissions. Up to 10.7Gbps speed.
Limiter Design • Voltage Gain • Bandwidth (Low End & High End) • Phase Response • DC Offset
Limiter Design by MOSFET • With ideal inductors, bandwidth is increased by 82% • With actual inductors, bandwidth is increased by 50% • But inductors consume substantial area
CDR Design(clock-and-data recovery) • Jitter Generation, Transfer, and Tolerance • Frequency Capture Range • Response to Long Runs • Flip-flop and Oscillator Speed
Frequency Acquisition • Capture range is typically a few percent. • VCO center frequency can vary substantially with process and temperature. • Must drive the VCO frequency toward the data rate before phase-locking can occur
Definition of Jitter • Synchronous networks such as the Synchronous Digital Hierarchy (SDH) and the Synchronous Optical NETwork (SONET) rely on highly accurate and stable synchronization to process data in and out of network elements. • Jitter is used to describe short term, non-cumulative variations of the significant instants of a digital signal from their ideal positions in time
CDR Jitter Generation • Jitter Generation: Peak-to-peak jitter produced by CDR circuit itself. Must typically remain below 0.1dB. To eliminate the jitter, there are several ways. (reference: Cheung, Jonathan, “Low Jitter Phase-Locked Loop”)
Prospects of CMOS Technology • The transit frequency of 0.13-um NMOS devices exceeds 100 GHz. • As with RF circuits, optical communication circuits can greatly benefit from CMOS technology. • The cost and integration advantages of CMOS manifest themselves in: • - Wave-Division Multiplexing Systems • - Multiple Transceivers for Bundle of Fibers • - Highly-Integrated Transceivers • CMOS at 40 Gb/s? Why Not?
Recommended Book • “Design of Integrated Circuits for Optical Communications”by Behzad Razavi • List Price: $144.15 • Half.com: $56.35
Reference Paper • Cheung, Jonathan, “Low Jitter Phase-Locked Loop” • “LXT16865 Transimpedance Amplifier (TIA)” http://www.intel.com/design/network/products/optical/phys/lxt16865.htm • Mauldin, Alan, “Global Internet Backbone Growth Slows Dramatically,” October 16, 2002 October 21, 2003 http://www.telegeography.com/press/releases/2002/16-oct-2002.html • Schmitt, Nicolas, “Jitter Measurements of Agilent Technologies OC-48 Optical Transceivers using the OmniBER718” http://ftp.agilent.com/pub/semiconductor/morpheus/docs/jitter_measurements2.pdf • “T1, T3, OC3, OC12, OC48 and OC192 Research Information” http://www.broadband-internet-provider.com/research-information.htm
Thank You for your time Questions?