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ELEC-2005 Electronics in High Energy Physics Spring term: Integrated circuits and VLSI technology for physics

CERN Technical Training 2005 ELEC-2005 Electronics in High Energy Physics Spring term: Integrated circuits and VLSI technology for physics Basic Analog Design Giovanni Anelli 15 March 2005 Part I Outline – Part I The MOS transistor: quick summary The MOS transistor DC characteristics

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ELEC-2005 Electronics in High Energy Physics Spring term: Integrated circuits and VLSI technology for physics

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  1. CERN Technical Training 2005 ELEC-2005Electronics in High Energy PhysicsSpring term: Integrated circuits and VLSI technology for physics Basic Analog Design Giovanni Anelli 15 March 2005 Part I

  2. Outline – Part I • The MOS transistor: quick summary • The MOS transistor • DC characteristics • Important formulas • Basic analog building blocks Giovanni Anelli - CERN

  3. The (N)-MOS transistor y z x DRAIN GATE SUBSTRATE Transconductance SOURCE Giovanni Anelli - CERN

  4. Linear and Saturation regions LINEAR REGION (Low VDS):Electrons (in light blue) are attracted to the SiO2 – Si Interface. A conductive channel is created between source and drain. We have a Voltage Controlled Resistor (VCR). G S D n+ n+ SATURATION REGION (High VDS):When the drain voltage is high enough the electrons near the drain are insufficiently attracted by the gate, and the channel is pinched off. We have a Voltage Controlled Current Source (VCCS). G S D n+ n+ Giovanni Anelli - CERN

  5. Voltage and Current sources RS Vout + Voltage source. Ideal if RS = 0. V Iout I Current source. Ideal if RS = ∞. RS Giovanni Anelli - CERN

  6. Drain current vs Drain voltage This is a real device measurement ! Output conductance Saturation region (VCCS) @ three different VGS Linear region (VCR) Giovanni Anelli - CERN

  7. Drain current vs Gate voltage This is also a measurement, same device. red High field (vertical and longitudinal) effects Linear region (green) and saturation region (red) Subthreshold region green Giovanni Anelli - CERN

  8. Log(IDS) vs VGS Exactly same measurement as before, but semi log scale red green WEAK INVERSION THRESHOLD VOLTAGE STRONG INVERSION SUBTHRESHOLD SLOPE LEAKAGE CURRENT Giovanni Anelli - CERN

  9. A few equations in saturation Weak Inversion Strong Inversion Giovanni Anelli - CERN

  10. Output conductance IDS ID’ DI ID Dashed lines:ideal behavior DV VD VD’ VDS G S D n+ n+ DL L The non-zero output conductance is related to a phenomenon calledchannel length modulation Giovanni Anelli - CERN

  11. Output conductance / resistance Drain-to-source current in saturation Output conductance Remember: l is proportional to 1/L Output resistance Giovanni Anelli - CERN

  12. gm / ID vs log (ID / W) Weak Inversion (W.I.) Strong Inversion (S.I.) W.I. M.I. S.I. Moderate Inversion (M.I.): No Equations Giovanni Anelli - CERN

  13. Outline – Part I • The MOS transistor: quick summary • Basic analog building blocks • Small-signal equivalent circuit • Common-Source Stage • Common-Gate Stage • Cascode Stage • Differential Pair • Current Mirrors • Differential Pair + Current Mirror Giovanni Anelli - CERN

  14. Our first circuit! VDD RD VDS VGS For a small signal: vds = -vgs*gm*RD Giovanni Anelli - CERN

  15. Small-signal equivalent circuit G D Valid only at very low frequencies No bulk effect S This equation fixes the bias point This equation defines the small signal behavior Giovanni Anelli - CERN

  16. Small-signal equivalent circuit D G S B And we should also add the series resistances… Giovanni Anelli - CERN

  17. Common-Source Stage (CSS) Small signal model in saturation G D Vout + gmVin Vin RD ro S VDD DC characteristic RD Small signal gain Vout Vin Small signal gain(with channel length modulation) ro The above results could also have been obtained directly from the small signal model Giovanni Anelli - CERN

  18. CSS Simulation - DC W = 100 mm L = 0.5 mm R = 100 W The maximum small signal gain is only –1.8!!! Giovanni Anelli - CERN

  19. CSS Simulation - DC Increasing the value of the load resistor to 1 kW we have W = 100 mm L = 0.5 mm R = 1000 W The maximum small signal gain is now –9.6. Giovanni Anelli - CERN

  20. CSS Simulation – Small Signal R = 1000 W gm = 9.6 mS We inject at the input a sinusoid with frequency 1 kHz, peak to peak amplitude 1 mV AND dc offset = 0.9 V. The DC offset is important to be in the right bias point. The input voltage is converted in a current by the transistor and then in a voltage again by the resistor. Giovanni Anelli - CERN

  21. CSS with Current Source load To increase the gain, we can use the output resistance of a transistor. T2 provides the DC current bias to T1, and has a high output impedance. The bias current is determined by Vb. VDD Small signal gain Vb T2 Vout This solution gives a much higher gain than the other solutions and has a better DC output swing, since Vout_max = VDD – VDS2_sat and Vout_min = VDS1_sat. Vin T1 N.B. The DC output level here is not well defined, we will need a feedback loop. Giovanni Anelli - CERN

  22. Diode-connected transistor Impedance seen looking into the source. VDD G, D ro gmVGS gmbVBS B ix S + ix vx + vx We have three resistances in parallel: 1/gm, 1/gmb and r0. This is true also if the gate is connected to a fixed potential which is not VDD. Giovanni Anelli - CERN

  23. Common-Gate Stage (CGS) In the Common-Source Stage the input signal is applied to the gate. We can also apply it to the source, obtaining what is called a Common-Gate Stage (CGS) Not considering channel length modulation (r0) for the moment VDD RD Vout Vb Vin The gain is slightly higher than the one of a CSS, since we apply the signal to the source. Giovanni Anelli - CERN

  24. Common-Gate Stage (CGS) Let’s now calculate the input impedance and the gain considering r0: VDD With the small-signal equivalent circuit we can easily obtain RD Vout Vb Vin The input impedance of a CGS is relatively low, but this only if the load impedance (RD) is low. Giovanni Anelli - CERN

  25. Cascode Stage (CascS) r01 The “cascade” of a Common-Source Stage (V-I converter) and of a Common-Gate Stage is called a “Cascode”. VDD REMINDER I RD Vout R1 R2 T2 Vb Vin T1 The gain is practically the same as in the case of a Common-Source Stage. Giovanni Anelli - CERN

  26. Cascode Stage Output Resistance One nice property of the cascode stage can be discovered looking at the resistance seen in the drain of T2. Rout With the small-signal equivalent circuit we can obtain T2 Vb Compared to a Common-Source Stage, the output impedance is “boosted” by a factor (gm2 + gmb2) r02. Vin T1 The disadvantage of the cascode configuration is that the minimum output voltage is now the sum of the saturation voltages of T1 and T2.It must therefore be used with care in low voltage circuits. Giovanni Anelli - CERN

  27. CascS with current source load To fully profit from the high output impedance of the cascode stage, it seems natural to load it with a high impedance load, like a current source. VDD Vb1 T3 Vout T2 Vb2 If r03 is not high enough, we can use the cascode principle to boost the output impedance of the current source as well. N.B. Remember that the DC output level here is not well defined, and that we will need a feedback loop. Vin T1 Giovanni Anelli - CERN

  28. Single-Ended vs Differential A single-ended signal is defined as a signal measured with respect to a fixed potential (usually, ground).A differential signal is defined as a signal measured between two nodes which have equal and opposite signal excursions. The “center” level in differential signals is called the Common-Mode (CM) level.The most important advantage of differential signals over single-ended signals is the much higher immunity to “environmental” noise.As an example, let’s suppose to have a disturbance on the power supply. VDD VDD RD RD RD Vout_SE Vout + Vout - Giovanni Anelli - CERN

  29. Single-Ended vs Differential The Common-Mode disturbances disappear in the differential output. Giovanni Anelli - CERN

  30. Differential Pair (DP) Vin1 Vin,CM Vin2 Vout2 Vout,CM Vout1 t VDD RD RD Vout1 Vout2 Vin1 Vin2 ISS The current source has a very important function, since it makes the sum of the currents in the two branches (I1 + I2= ISS) independent from the input common mode voltage.The output common mode voltage is then given by: Giovanni Anelli - CERN

  31. Differential Pair (DP) Vout1 - Vout2 RD ISS Vin1 - Vin2 - RD ISS VDD VDD Vout2 Vout1 RD RD Vout1 Vout2 VDD - RD ISS Vin1 - Vin2 Vin1 Vin2 ISS N.B. The small signal gain is the slope of this plot Giovanni Anelli - CERN

  32. DP small signal gain This circuit can be easily analyzed assuming that the point P is AC grounded. In this case, we have 2 Common-Source Stages! VDD RD RD Vout1 Vout2 Vin1 Vin2 T1 T2 P Vb T3 Giovanni Anelli - CERN

  33. Differential Pair with MOS loads To analyze the two circuits we can now make use of the half-circuit concept and profit from all the results obtained up to now. VDD VDD T4 T4 T3 T3 Vb Vb Vout2 Vout1 Vout2 Vout1 Vin2 Vin2 Vin1 Vin1 T2 T2 T1 T1 ISS ISS Giovanni Anelli - CERN

  34. Cascode Differential Pair And, of course, the gain can be boosted using common-gate stages. VDD T8 T7 Vb3 Vb3 T6 T5 Vb2 Vb2 Cascode stages were used a lot in the past, when the supply voltages were relatively high (few volts). In deep submicron technologies they are used with more care. Vout1 Vout2 Vb1 Vb1 T4 T3 Vin1 Vin2 T2 T1 ISS Giovanni Anelli - CERN

  35. Current mirror (CM) We suppose that all the transistors have the same m, Cox and VT.l is the same if the transistors have the same L VDD IREF I1 WRLR W1L1 GND To have an exact replica of the reference current, we have to make the transistor identical AND they must have the same VDS. When this is not possible, choosing long devices reduces the effect of l.Precise current ratios can be obtained playing with the ratio between the transistor widths (not the lengths!). Giovanni Anelli - CERN

  36. Cascode current mirror (CCM) VG3 must be fixed so that VD1 = VD2. Making L1 = L2 and therefore having l1 = l2, we obtain that the current I3 practically does not depend on the voltage VD3. Of course, all the devices must be in saturation (the circuit is not suitable for low voltage applications). I3 VDD VD3 W3L3 IREF VG3 VD1 VD2 W1L1 W2L2 GND Important: L3 can be different from L1 and L2. How do we fix VG3 so that VD1 = VD2 ? Giovanni Anelli - CERN

  37. Cascode current mirror (CCM) VDD Transistor 4 does the job here! Transistors 1 & 2 decide the current ratio. Transistors 3 & 4 fix the bias VD1 = VD2. These results are valid even if transistors 3 & 4 suffer from body effect. IREF I3 VD3 W4L4 W3L3 VD1 VD2 W1L1 W2L2 GND The problem of this current mirror is that VD3 > VDS3 + VGS2. Giovanni Anelli - CERN

  38. Differential Pair + Active CM Current mirrors can also process a signal, and they can therefore be used as active elements. A differential pair with an active current mirror is also called a differential pair with active load. The current mirror here has also the important role to make a differential to single-end conversion! VDD Common Mode Analysis T3 T4 Vout T2 T1 Maximum output excursion Vin T5 Vb Giovanni Anelli - CERN

  39. Differential Pair + Active CM Let’s now calculate the small-signal behavior, neglecting the bulk effect for simplicity. The circuit is NOT symmetric, and therefore we can not use the half-circuit principle here. As a first approximation, we can consider the common sources of the input transistors as a virtual ground. The small-signal gain G can be seen as the product of the total transconductance of the stage and of the output resistance. VDD T3 T4 iout + Vout T2 T1 ISS Giovanni Anelli - CERN

  40. CERN Technical Training 2005 ELEC-2005Electronics in High Energy PhysicsSpring term: Integrated circuits and VLSI technology for physics Basic Analog Design Giovanni Anelli 15 March 2005 Part I

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