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Overview

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Overview

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  1. Design and System Driver ChaptersITRS ConferenceJuly 2004San Francisco, CAEurope Ralf Brederlow, Wolfgang EckerJapan Ichiro Yamamoto, Tamotsu Hiwatashi, Koichiro Ishibashi, Yoshimi AsadaTaiwan Charlie ChenU.S.  Juan-Antonio Carballo, Andrew Kahng, Valeria Bertacco

  2. Overview • Why design • Design cost is still a threat to economic viability • Design is a key lever to address power challenge • Design is the missing link in manufacturability • Major focus areas • Derive quantitative, detaileddesign technology requirements and solutions • Detailed tables • Address Design-Manufacturinginterface challenges • New section and model

  3. Design TWG Chapters Productivity Power DFM Interference Reliability • Design Chapter • Crosscutting challenges (design cost) • DT challenges • Design Process • System-level Design • Logical, Circuit, and Physical Design • Design verification • Design Test • Additional / Cross-cut issues • System Driver Chapter • Market Drivers • System on Chip Driver • SOC Multi-technology • SOC High-performance • SOC Low-cost, Low-power • Microprocessor (MPU) Driver • Mixed-signal Driver • Embedded Memory Driver

  4. 2004-2005 ITRS Design Goals

  5. Design Chapter Tables • General Design Requirements Table (2004) • Updated numbers • New rows (area density improvement) • Detailed explanation of each row (footnote) • General Design Solutions Table (2004) • New table • New solutions after 2008 • Outline future (2005) decomposition for detailed tables • Currently design process-based • Size ~ 50 requirements, 50 solutions • Will map to grand challenges

  6. Design Helps – Not Enough • Improvement beyond scaling • Still reaching a power management crisis

  7. Design Cost  Reuse/ESL Are Critical What’s Next? ES Level Methodology Very large block reuse Intelligent testbench Large block reuse Small block reuse Tall thin engineer IC implem. tools In-house P&R $10,000 $1,000 $100 Design cost ($M) $10 $1 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010

  8. New General Design Solutions Table 2004 2007 2010 2013 2016 2019 2003 2005 2006 2008 2009 2011 2012 2014 2015 2017 2018 Technology Node hp90 hp65 hp45 hp32 hp22 hp16 Continuous Improvement This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Research Required Qualification/Pre-Production Development Underway Intelligent testbenches ESL Design Very large block reuse System power mgt. DFM (DFY) Ultra large system (HW+SW) reuse

  9. SW Cost needs to be Included Chip/circuit/physical design Chip integration Product cost Labor Verification, test SW development EDA integration & support Development R&D EDA licenses Test chips Infrastructure Manufacturing Marketing, sales Depreciation/amortization General, administrative Key: design/development costs other costs Maintenance, service Financial Source: ITRS cost tree

  10. Software “Design” Versus Other Costs • More embedded software designers needed, and used World’s designers (thousands) Source: VDC Source: VDC

  11. SW Cost Model - Methodology • Identify target SoC for cost model analysis • SoC for mobile platform must be a good target • Get and collect information for target SoC • Required functions, performance • Roadmap for the target application • Develop SW roadmap for the target SoC • Define the layer of SW to be discussed as a SoC Cost model • Identify required SW associated with the required functions and performance for the target SoC

  12. New DFM Section –Outline • INTRO • DFM CHALLENGES -- NEAR TERM (>45 NM) • MASK COST • DATA EXPLOSION • LIMITATIONS OF LITHOGRAPHY HARDWARE RESOLUTION • VOLTAGE SUPPLY AND THRESHOLD VARIABILITY • BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY • HETEROGENEOUS COMPONENTS (AMS, MEMS, ERAM) • LEAKAGE AS A LIMITER OF MANUFACTURABILITY • VARIABILITY • DFM CHALLENGES -- LONG TERM (<45 NM) - UNCONTROLLABLE CD AND DOPING VARIABILITY - EXTREME DEVICE AND CIRCUIT VARIABILITY • RET-awareness IN DESIGN • PACKAGE, SYSTEM, AND SW VARIABILITY • BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY • DESCRIPTION OF VARIABILITY MODEL

  13. Multi-Level Variability Roadmap Framework(Design – CSTNSG) • Abstraction level of variations 1. Circuit/chip Timing, power 2. Device Vt, Ioff 3. Physical Le, NA Vdd, T

  14. Data Flow • Δ outputs = model (Δ inputs) • Flexible, based on published models • Variability (delta) = Statistical spreadsheet “simulation” Performance (delay) Power (energy) “Gate” delay (power) “Wire” delay (power) Intermediate parameters Intermediate parameters (Vdd, T) Rsheet Vt Leff tOX NA Weff L W t tILD

  15. Illustration of Model Result 60% 50% 40% • (Work in Progress!!) • Validation • Inputs from ITRS tables • Statistical independence • Power consumption • Simplicity of circuit 30% Performance variability 20% 20% CD variation 10% CD 10% variation 0% 2000 2005 2010 2015 2020

  16. Design-Manufacturing Co-Roadmapping • Invest in variability reduction or in design productivity? 6.0 Normalized ROI (10% more variability) 5.0 Normalized ROI (base) 4.0 Overall Normalized ROI 3.0 2.0 Two alternatives, to duplicate return 1.0 0.0 0% 10% 20% 30% 40% 50% Design Productivity improvement Source: IBM model

  17. Detailed Tables (2005) • Approach • Take current preliminary rows  ~50 reqs + solutions • Map to grand challenges  ~5 tables General Selection Productivity Power DFM Interference Reliability Mapping Design process System design Logic/circuit Physical D Design verification Design Test DFM (new)

  18. Identify Mapping Drivers-Applications • Issue: roadmap mostly focused on “fabrics” • Other roadmaps more app- or product-focused • Actions being taken • Constant connection with NEMI roadmap • Mutual mapping being developed between drivers • Exact alignment of ITRS’s and NEMI’s market drivers • Content changed for 2005

  19. Mapping Approach Drivers Applications (NEMI) Medical Automotive Office Network Defense Portable SIP/SOC (ITRS) SIP/SOC A4 A3 A2 A1 Architectures Chips /Fabrics (ITRS) MPU Memory DSP AMS Source: ITRS Design TWG

  20. NEMI-ITRS Potential References

  21. Verification  Current landscape Technology Formal Verification Semi-formal verification Simulation-based methods Emulation/ rapid prototyping Real chip Module Sub-system System Applicationsoftware

  22. Verification  Challenges considered keeping structure update items

  23. Other Content (2005) • SiP  to-be-added content • Alignment with Assembly/Packaging • Definition of tool and flow challenges • DSP / MCU • Not much content at this time • DSP / MCU have their own particular requirements

  24. Summary • Major 2004-2005 focus areas • Derive quantitative, detaileddesign technology requirements and solutions • Detailed tables • Address Design-Manufacturinginterface challenges • New section and model • Expected results • New color tables • New content • Better alignment with other chapters and roadmaps

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