Real time DSP

1. Real time DSP Professors: Eng. Julian Bruno Eng. Mariano Llamedo Soria

2. DSP fundamentals Number representation and word-length effects.

3. Recommended bibliography • RG Lyons, Understanding Digital Signal Processing. Prentice Hall 1997. • Ch9: Digital Data Formats and their effects. • SW Smith, The Scientist and Engineer’s guide to DSP. California Tech. Pub. 1997. • Ch4: DSP software. • VK Madisetti, DB Williams. Digital Signal Processing Handbook. CRC Press. • Ch3: Finite Wordlength Effects. • SM Kuo, BH Lee. Real-Time Digital Signal Processing. John Wiley and Sons. • Ch 3.4 to 3.6: DSP Fundamentals and Implementations Considerations. • NOTE: Many images used in this presentation were extracted from the recommended bibliography.

4. Fixed point representation – Two’s complement system Sign bit 011= 3 101=-3 Range -2N-1 to (2N-1-1) for N data bits DRdB = 20log(lv/sm) DRdB: Dynamic Range in dB lv: Largest possible value sv: Smaller possible value DRdB= 6.02dB . (N-1) • One bit for sign, N-1 for number representation. • Very popular system, widely used. • Samelogic for sum and subtraction.

5. Q formats Fractional representation is equivalent to integer representation. Fractional dot could be placed arbitrarily anywhere. Most widely used formats are Q15 and Q31. Dynamic range is exactly the same than their integer counterparts “short” and “int” C language types. Q15 means 15 bits for fractional part (aka 1.15) Q31 means 31 bits for fractional part (aka 1.31) Q12 means 12 bits for fraction 3 bits for integer /2N: moves dot N places left x2N: moves dot N places right Decimal equivalency for 1.X formats DRQ15 = 6.02*15 = 90.3 dB DRQ31 = 6.02*31 = 186.62 dB Range -1 to 1-(2-N) for N fractional bits

6. Sum in Two’s complement Integer Fromat Overflow ! Q3 Fromat Overflow !

7. Sum in Two’s complement Different Formats • For C=A+B, where • A is in P.Q format • B is in R.S format • The result C is in max(P,R).max(Q,S) format

8. Multiplication in Two’s complement Fractional Format Q3 Integer Format Xor Xor Sign extension • For C=AxB, where • A and B are B bits wide, C is 2B bits wide.

9. Multiplication in Two’s complement Different formats Xor Xor Sign extension

10. Multiplication in Two’s complement. Conclusion. • In conclusion, for C=A*B, where A and B are words of N bits, and • A is in P.Q format • B is in R.S format • The result’s is in (P+R).(Q+S)

11. Multiplication in Two’s complement. Examples. • A=1011 • B=0110 • The result is always the same. • In 2.6 format, as numbers are <1, the integer part is never used. Int Fract

12. Two’s complement arithmetic. Conclusions. • Addition/Accumulation requires representation in the same format (sign extension, zero padding). • Multiplication result is independent of the format representation, as long as the result place the fixed point in the right place. • ADSP2100 family always assume fractional multiplication, whereas modern families can flag (IS) integer multiplication.

13. Dynamicrange constraints For non integer Q formats, multiplying large sequence of numbers cause loss of precision, but never overflow. For non integer Q formats, summing large sequence of numbers could cause overflow. Dynamic range is closely related with the two previous statements. The greater dynamic range, the smaller probability that overflow or loss of precision could happen. Remember that most DSP algorithms multiply and sum very often, so special care must be taken to prevent overflow or loss of precision.

14. Avoiding overflow • Always use the maximum capability (guard bits) of the accumulators during internal calculations. • Only round (or truncate) the final results to the final data size and format if possible. • There is (almost) no lost of precision when handling internal calculations with guard bits.

15. 0.9.β 0.8.β Avoiding overflow • Scaling down a signal is the most effective technique to prevent overflow. • Scaling down always implies loss of precision. • Both scaling down and guard bits techniques must be used in order to avoid overflow. • Always is more convenient to scale down system’s coefficients instead of signals. System Scale Signal

16. Avoiding overflow • Scaling down always reduces SNR. • It is possible to use an absolute safe or a more relaxed criteria to choose βvalue. • Many times it is preferable to use different Q fractional formats within an algorithm. • As overflow is very probable to happen in fixed point processors, special effort should be taken when coding algorithms and debugging. Effect of β in SNR Never overflows For example adopting β=0.5 implies a 6.02 dB decrease of SNR. This is equivalent that dividing by 2, rotating 1 time to the right, or losing 1 bit of resolution. More relaxed scaling

17. Minimizing overflow effects • Always use saturating arithmetic. • In case overflow occurs, decrease the probability that an oscillation occurs. Without saturation arithmetic With saturation arithmetic

18. Example of an overflow oscillation We have the following output For a system defined by: and an input: being the overflow rule: having a 4 bit word length, and no saturation arithmetic

19. Quantization word-length effects • The codec and system’s coefficients are the main generators of quantization noise. • Codec’s noise can be thought as a uniformly distributed PDF between –LSB/2 and LSB/2. • The SNR of an ADC is proportional to the word-length and the loading factor.

20. Quantization word-length effects • When defining a system in term of its coefficients, the finite precision affect the behavior of the system itself. • Though there is a grid of possible locations where system’s poles can be placed. • This grid depends first of the word-length and second of the structure adopted to implement of the system. Complex conjugated two poles band pass And its difference equation

21. Quantization word-length effects • There are structures are less sensitive to coefficient quantization. • There is a trade-off between efficiency and sensibility to coefficient quantization.

22. Floating point representation • This form of representation overcomes limitations of precision and dynamic range of fixed point. • This format segment data in sign, exponent and mantissa. • Mantissa is represented as a fixed point number. • Exponent is represented in binary offset format. • The greater the be the larger the dynamic range. • The greater the bm the larger the precision. • There is a trade off between bm and be, and the best balance occur at be≈b/4 and bm≈3b/4.

23. Floating point representation (I) • IEEE P754 is the most widely used floating point format. • As the point is floating, a process called normalization is performed in order to use the full precision of bm bits, while the exponent is adjusted properly. • Floating point arithmetic usually requires lot of logical comparisons and branching, so software emulated floating achieves low performance • Floating point DSPs implements in hardware all arithmetic handling, so these DSPs outperforms their fixed point counterparts in ease of use and performance (of course being more expensive too).

24. Floating point representation (II)

25. Unused Normalized numbers ( 1,f 2e-127) 0 2-126 2-125 2-124 2-123 Gap = 1.4e-45 Gap = 2.8e-45 0 2-126 2-125 2-124 2-123 Min. Positive Normalized 0 00000001 00000000000000000000000 Denormalized numbers ( 0,f 2-126) Gap = 1.4e-45 Min. Positive Denormalized 0 00000000 00000000000000000000001 Normalized & Denormalized numbers (32-bit format )

26. MULTIPLY No No Subtract bias Add exponents ¿X = 0? ¿Y = 0? Yes Yes Report overflow Yes Exponent overflow? Z 0 No RETURN Yes Report underflow Exponent overflow? No Multiply significands Normalize RETURN Round Multiply

27. DIVIDE No Subtract exponents No Add bias ¿X = 0? ¿Y = 0? Yes Yes Yes Report overflow Exponent overflow? Z 0 Z  No Yes RETURN Report underflow Exponent underflow? No Divide significands Normalize Round RETURN Division