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4 Bit Serial to Parallel Data Stream Converter. Vinaya Anne Kristy Lypen Michael Scheel Victor Zavaleta. Design Specifications . Convert a serial data stream every 4 clock cycles to a 4 bit parallel stream Operate at the positive edge of the clock Drive a 10pF load at 25MHz
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4 Bit Serial to Parallel Data Stream Converter Vinaya Anne Kristy Lypen Michael Scheel Victor Zavaleta
Design Specifications • Convert a serial data stream every 4 clock cycles to a 4 bit parallel stream • Operate at the positive edge of the clock • Drive a 10pF load at 25MHz • Minimize skew • Area less than 40mil2
Parameters • D Flip-Flop • WnCaclulated = 10.4m m WnActual = 23.2m m • WpCaclulated = 27.6m m WpActual = 27.6m m • Based on CLoad of Output = 179f F • Buffer • Total Area: 1750 x 600 mm Power: 400mW
Block Diagram P A R A L L E L S E R I A L D Flip Flop Latch / Buffer Schmidt Trigger D Flip Flop Frequency Counter D A T A D A T A D Flip Flop