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A 4 bit Serial to Parallel Converter

A 4 bit Serial to Parallel Converter . Jason Baechler Benjamin Liu Forozan Amely Trang Nguyen. Introduction. Our project is to design a 4 bit serial to parallel data stream converter. Project Specification. 25Mhz Clock 50% clock duty cycle Power is less than 500 mW Vth = 2.5 V

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A 4 bit Serial to Parallel Converter

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  1. A 4 bit Serial to Parallel Converter Jason Baechler Benjamin Liu Forozan Amely Trang Nguyen

  2. Introduction • Our project is to design a 4 bit serial to parallel data stream converter

  3. Project Specification • 25Mhz Clock • 50% clock duty cycle • Power is less than 500 mW • Vth = 2.5 V • Output Buffer drives 10pF load • Area is less than 40 mm^2

  4. Schmitt Trigger • Reduces the noise at the input • Wnf = 8 um • Wpf = 225 um

  5. Schmitt Trigger

  6. Schmitt Trigger

  7. Schmitt Trigger

  8. Clock • to take a serial stream at 25Mhz: - clock period = 40ns - for minimizing the skew, a fat bus was used for clock - Pick up 1/10 of the clk period for the Tf and Tr for 4ns

  9. Counter Waveform

  10. DFF Schematic

  11. DFF Layout

  12. DFF Waveform

  13. Shift Register Schematic

  14. Shift Register Layout

  15. Shift Register Waveform

  16. Buffer Schematic

  17. Buffer Test Bench

  18. Buffer Layout

  19. Buffer Waveform

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