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Intro To Xilinx Foundations

Intro To Xilinx Foundations. How to Setup a Basic Project. What Will Be Covered. This Presentation Will Demonstrate: Creating a new Xilinx project Using the HDL wizard Synthesizing and creating a macro Schematic flow macro organization Simulation Keeping track of your work.

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Intro To Xilinx Foundations

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  1. Intro To Xilinx Foundations How to Setup a Basic Project

  2. What Will Be Covered • This Presentation Will Demonstrate: • Creating a new Xilinx project • Using the HDL wizard • Synthesizing and creating a macro • Schematic flow macro organization • Simulation • Keeping track of your work

  3. Creating a Project • When you first open Xilinx you will usually be presented with this screen • Click on create a new project and then OK • If you open into a project • Click file->new project

  4. Setting up a Project • You have chosen to create a new project • Name your project • Try to keep names short, older versions of Xilinx have problems with long names • 8 characters • Leave the type on its default • For simplicity choose schematic flow • For your designs you wont need to worry about which part you target, leave on default

  5. Working With Your Project • This is the basic Project Manager

  6. Entering Source Code • To create a source code file • Click on the HDL icon shown above • The easiest way is to use the wizard • Some versions of Xilinx have problems with the pointers created by a new document • Using the wizard ensures that these pointers are all correct and you are compiling from the correct source file • After selecting HDL wizard Click OK

  7. The HDL Wizard • On the first wizard screen just click next • Choose your language -> • Name your file \/

  8. The HDL Wizard • The wizard will automatically declare your ports for you • Click New to add a port • Type in the name • Choose I / O • Click New again to confirm • After all are added • Click Finish

  9. The HDL Wizard Output

  10. Enter Your Source Code • Now that the wizard is done • Enter your statements and comments • Some Things to Note • Only the ports on the module appearing first in the code will be on the macro • Sometimes as you make small changes in code the results will not be noted in simulation • To avoid this you must: • Create an error • Synthesize to find the error • Fix the error • Re-synthesize

  11. Syntax Check and Synthesis • Throughout your design you can check your syntax • From the Synthesis menu choose check syntax • Once your design is ready • You must next synthesize your design • From the synthesis menu choose synthesize

  12. Macros • To work in schematic flow you must generate a Macro • Once you have successful synthesis • From the project menu • Click on Create Macro the first time • Each time you want to update the project macro click on update macro just below it • Once you have successful macro creation • You can place your macro on a schematic to interface with other macros and simulate

  13. Some Nice Features • Not only can you enter your source code • Xilinx includes a syntax help feature • From tools menu choose language assistant • The language assistant will provide simple example blocks of code • Some examples of basic logic parts are also included

  14. Language Assistant

  15. Creating a Schematic • Now you have to go back to the project manager • Look where you clicked on HDL and find the third icon (and gate) • Click on that to open a new schematic

  16. Schematic Tool Bar • Selection tool-select portions of schematic • Hierarchy tool-view the lower hierarchy • Part tool-get parts from the library • Draw wire-connect ports with wires • Draw bus-connect vectors with busses • Single wire from a bus • Labeled wire • Hierarchy connector-mark as upper level port • Draw Line-draw boxes on the schematic

  17. Placing Parts • Click on the part tool • The parts selection will appear • Find your library (project name) • Listed in alphabetical order • Under your project is every macro • Click on the macro name to place the part

  18. Your Schematic Part • Below is your macro on the schematic • The skinny lines represent wires • The fat lines represent busses • Use the appropriate tool to connect

  19. Busses And Wires • For your simulator to recognize ports you must place wires • Use the wire tool to draw an empty wire from each port • Double click on the wire with the selection tool to enter a label • These labels are used in the simulator to construct waveforms

  20. Probing for Simulation • In the upper tool bar you’ll see two tools the probe and simulator tool (above) • Click on the probe tool (left) to determine which outputs you desire to watch • Place a probe by clicking on the port • This will now be shown in the sim • To start the simulator • Click the SIM tool after probes are placed • You can place other probes once the the simulator is open so don’t worry if you forget one

  21. The Simulator Window • Below is what you see for the simulator • To create a simulation script • From the tools menu choose script editor • Some notes: • Simulator by default initializes all values to zero • Functional simulator assumes ideal rise and fall • For more accurate timing analysis use timing simulator

  22. The Script Editor • When you choose script editor cancel this wizard (more trouble than its worth)

  23. Basic Script Syntax • Declare a stepsize in ns, us, ms (time) • Identify your clock with keyword clock • Input your waveforms to provide the necessary stimulus • Use keyword wfm • Define in terms of time for example • wfm reset @0ns=1 @10ns=0 • Define as many as necessary • Define the number of cycles to run • Use the keyword cycle followed by number • It is easier to create stimulus modules like counters or test data for memories on the top level schematic • By this method you only need to provide the basic waveforms for simulation

  24. Script to Check the Counter Stepsize 10ns Clock clk 0 1 Wfm reset @20ns=1 @40ns=0 Wfm ena @0ns=0 @20ns=1 Cycle 100 • Notes: • To comment use the | • Use the first icon to run the sim • Use the second to restart after a run • Use the third to stop a sim in mid run • There is a macro assistant in the tools menu to help with the script file syntax

  25. The Simulation Results • Some helpful hints • If you want to view a bus in decimal rather than hex • Right click on the bus name go down to the bus menu and find display decimal • To delete signals select those to delete and right click, go to delete signals and click selected

  26. Keeping Track of Your Work • Archiving a project • Because there are so many files for a Xilinx project you must archive them to move from machine to machine • From the file menu choose archive project and follow the wizard • This creates a zip file of your project • From the file menu you can restore a project as well onto any machine with Xilinx software

  27. Congratulations • Feel free to reference this presentation as often as necessary at • http://www.cse.fau.edu/~sbowser • Click on school and find the link at the bottom • This may seem like a lot but after a few projects it becomes second nature

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