M i s m a t c h Modeling of MOS Transistors for Deep Sub-micron Technologies

1. Mismatch Modeling of MOS Transistors for Deep Sub-micron Technologies Rasit Onur Topaloglu rtopalog@cse.ucsd.edu University of California at San Diego Computer Science and Engineering Department La Jolla, CA, 92093, USA

2. Outline -Mismatch at transistor, circuit and VLSI levels -Modeling Challenges and Requirements in Deep Sub-Micron -Optimizations to Avoid Mismatch -Past and Present Mismatch Modeling Approaches: -Electrical & Empirical Models -Layout-based Models -BSIM-based Models -Physics-based Models -Insights for Future Models for Mismatch -Summary & Conclusions

3. Semiconductor Manufacturing Steps silicon dioxide silicon • Wafer is oxidized photoresist silicon dioxide • Wafer is covered with photoresist silicon photomask photoresist • A photomask is placed on wafer silicon dioxide silicon silicon • Wafer is created

4. Semiconductor Manufacturing Steps photoresist • Unexposed regions dissolved silicon dioxide silicon photoresist silicon dioxide • Unprotected oxide etched silicon silicon dioxide • Photoresist removed. Wafer is ready for doping silicon UV radiation photomask photoresist silicon dioxide • Wafer is exposed to ultra-violet (UV) radiation silicon

5. Possible Causes of Mismatch silicon dioxide doped regions • Doping creates n or p-type wells • Mismatch is caused by variations in the processing stagesex. photomask misalignment, difference in doping gradients, etc. • These variations can depend on the process (PVE), or they can be random effects (RE) • Mismatch negatively influences the design, which assumes accurate matching of electrical parameters between matched transistors doping silicon dioxide • Wafer is doped silicon

6. ID quadratic increase Vth VGS ID VG GND VDD L Increasing VGS G S D ID Drain current formula: VDS Physical view Transistor Operation and Mismatch VDD Vth=threshold voltage D=drain G=gate S=source V=voltage I=current L=channel length W=channel width n=channel mobility Cox=oxide capacitance ID D G VG VG VDS S VGS GND Schematic view of transistor Mismatch = variation in drain current of matched transistors

7. Proper circuit operation requires precision matching of certain transistors Mismatch = variation in drain current of matched transistors • Mismatch most important in analog circuits Impact of Mismatch on a Circuit • Analog circuits implement a linear function within a local input space by strictly optimizing circuit parameters M=transistor i=input G=gain VOUT Vi1 M1 M2 Vi2 A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2)

8. Mismatch = variation in drain current of matched transistors • Mismatch most important in analog circuits Impact of Mismatch on a Circuit • Analog circuits implement a linear function within a local input space by strictly optimizing circuit parameters W=width VOUT Vi1 W1=300m W2=300m Vi2 A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2) • Proper circuit operation requires precision matching of certain transistors

9. Mismatch = variation in drain current of matched transistors • Mismatch most important in analog circuits Impact of Mismatch on a Circuit • Analog circuits implement a linear function within a local input space by strictly optimizing circuit parameters Vth=threshold voltage G=gain VOUT Vth1=0.7V Vi1 Vth2=0.7V Vi2 A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2) • Proper circuit operation requires precision matching for certain transistors

10. Mismatch = variation in drain current of matched transistors • Mismatch most important in analog circuits Impact of Mismatch on a Circuit • Analog circuits implement a linear function within a local input space by strictly optimizing circuit parameters Id=drain current VOUT Id1=1mA Vi1 Id2=1mA Vi2 A current mirror operational amplifier realizing the function Vout=G(Vi1-Vi2) • Proper circuit operation requires precision matching for certain transistors

11. 300+2+-2 300+2+1 G G 300 300 300 303 PVE RE PVE RE W1when W2=W1 W1when W2=300 Process Variations and Mismatch PVE=process variation effects RE=random effects W1 W2 G Nominal : 300 300 100 PVE+RE causing mismatch: 303 303 102 297 297 98 PVE+RE not causing mismatch: 303 300 99 297 300 90 VOUT Vi1 Vi2 Iref • Mismatch deteriorates circuit performance, in the limit, causes the circuit to escape optimal operating region • PVE and RE’s add up; they may or may not create a mismatch that effects circuit operation according to specifications

12. Impact of Mismatch on VLSI Design Mismatch causes soft errors (reduction in gain, higher output R) -Yield loss Critical mismatch necessitates re-design -Increased time to market Mismatch effects are not easily predictable -Optimization of circuit without accurate consideration of mismatch is barely lost time • We need to design for mismatch • We need to estimate effects of mismatch : both require models

13. Behavioral level design and simulations Select architecture and technology SPICE simulations Manual design Optimizations SPICE simulations Optimizations Test & diagnosis after production Why Mismatch Models Necessary for Analog Design Flow? Costly redesign needed due to late observation of mismatch effects

14. Behavioral level design and simulations Select architecture and technology Manual design SPICE simulations Optimizations Test & diagnosis after production Why Mismatch Models Necessary for Analog Design Flow? Manual design Costly redesign needed due to late observation of mismatch effects Essential to help model mismatch as soon as possible so as to accomplish heavy reduction in number of iterations

15. Outline -Mismatch at transistor, circuit and VLSI levels -Modeling Challenges and Requirements in Deep Sub-Micron -Optimizations to Avoid Mismatch -Past and Present Mismatch Modeling Approaches: -Electrical & Empirical Models -Layout-based Models -BSIM-based Models -Physics-based Models -Insights for Future Models for Mismatch -Summary & Conclusions

16. Mismatch Predictive models Manually applicable models Accurate models for simulation Models for Test and diagnosis Model Requirements for each Step of the Design Flow Behavioral level design and simulations Select architecture and technology Manual design SPICE simulations Optimizations Test & diagnosis after production

17. actual pdf Vb1 Vb2 Bandgap reference circuit 99 % falls in this range Vb3 Iref OpAmp Iref Current mirror Worst-Case Estimations Fail in Deep Sub-Micron Worst-case limits for an output parameter • Worst-case propagation between blocks results inoverestimationof errors • Designing while considering such large variations impossible in DSM • Correlationsbetween parameters accentuate this error New models should avoid worst-case estimations

18. The Increasing Importance of Random Effects PVE tox (x40nm) tox (x4nm) newer technology Wafer radius Wafer radius RE Fabrication accuracy cannot keep up with feature size shrinkage rate, as: • Errors occurring from diffusion cause PV distributions that have similar    across different technologies • Mismatch groups closer than ever before, therefore: REs assume increased importance compared to previous technology New models should be able to consider random effects

19. Outline -Mismatch at transistor, circuit and VLSI levels -Modeling Challenges and Requirements in Deep Sub-Micron -Optimizations to Avoid Mismatch -Past and Present Mismatch Modeling Approaches: -Electrical & Empirical Models -Layout-based Models -BSIM-based Models -Physics-based Models -Insights for Future Models for Mismatch -Summary & Conclusions

20. Layout Optimizations A B B A tox=4.2nm tox=4.2nm tox=4.1nm tox=4.1nm tox=4.0nm tox=4.0nm Common centroid layout style iso-parameter contours for a physical parameter such as tox • Statistical average of a parameter would differ a lot on matched transistors without optimizations causing significant mismatch • Layout optimizations try to disperse the effects of on-chip gradients between matched transistors A and B equally tox=oxide thickness A B standard layout style

21. Criticism of Layout Optimization iso-parameter contours for a physical parameter such as tox tox=4.2nm tox=4.1nm A B B A tox=4.0nm Common centroid layout style +Sufficient for minimal to moderate matching -Suffers linear optimization limitations as transistors rectangular, yet physical parameter distributions have curves -Connecting gates, or avoiding from deteriorating effects of other blocks on layout may be problematic -Not quite suitable for matching ratios other than unity

22. Circuit Optimizations y[n] x[n] PSD frequency PSD=power spectral density DAC=digital to analog converter A Digital-to-Analog Converter (DAC) x1[n] y1[n] 1-Bit DAC y2[n] 1-Bit DAC Thermometer Encoder b x[n]  . . y[n] . . 1-Bit DAC y2b[n] x2b[n] • The circuit implements an ideal staircase transfer function between input and output • Mismatch within DAC’s cause a related performance parameter, PSD, to fail specifications I. Galton and P. Carbone, “A Rigorous Error Analysis of D/A Conversion with Dynamic Element Matching,” IEEE TCAS-II, 1995

23. Circuit Optimizations • Scrambler randomly selects 1-Bit DACs to be used in computation A Low Harmonic DAC PSD x1[n] y1[n] 1-Bit DAC y2[n] 1-Bit DAC Thermometer Encoder b x[n] Scrambler  y[n] . . frequency . . . . 1-Bit DAC y2b[n] x2b[n] I. Galton and P. Carbone, “A Rigorous Error Analysis of D/A Conversion with Dynamic Element Matching,” IEEE TCAS-II, 1995

24. Circuit Optimizations • Mismatch in 1-Bit DAC blocks averaged, compensating deteriorating effects of mismatch on distortion A Low Harmonic DAC PSD x1[n] y1[n] 1-Bit DAC y2[n] 1-Bit DAC Thermometer Encoder . . b x[n] Scrambler  y[n] frequency . . . . 1-Bit DAC y2b[n] x2b[n] • Scrambler randomly selects 1-Bit DACs to be used in computation I. Galton and P. Carbone, “A Rigorous Error Analysis of D/A Conversion with Dynamic Element Matching,” IEEE TCAS-II, 1995

25. Criticism of Circuit Optimizations A Low Harmonic DAC x1[n] y1[n] 1-Bit DAC y2[n] 1-Bit DAC Thermometer Encoder . . b x[n] Scrambler  y[n] . . . . 1-Bit DAC y2b[n] x2b[n] +May be the best way to optimize for a single parameter -Architecture specific, hence requires design time -It is usually necessary to optimize a circuit for more than one parameter

26. Outline -Mismatch at transistor, circuit and VLSI levels -Modeling Challenges and Requirements in Deep Sub-Micron -Optimizations to Avoid Mismatch -Past and Present Mismatch Modeling Approaches: -Electrical & Empirical Models -Layout-based Models -BSIM-based Models -Physics-based Models -Insights for Future Models for Mismatch -Summary & Conclusions

27. Derivation of Vos starts with equating drain voltages: R1 R2 Vos=offset voltage R=resistance ID1 ID2 Vos + + VGS1 VGS2 Drain current formula: - - Iref Differential stage Electrical / Empirical Parameter-based Mismatch Modeling • Classical ad-hoc approach by designers • Threshold voltage mismatch is the most common model • Worst-case conditions algebraically calculated for parameters Ex:Mismatch modeled at input as common-mode offset voltage for a differential pair B. Razavi, “Analog CMOS Integrated Circuits,” McGraw-Hill, 2000

28. R1 R2 • Terms with  come from first order Taylor series expansion ID1 ID2 Vos + VGS1 VGS2 • Assumption: Independence between parameters - - • By adding Vos, mismatch caused degeneration of some parameters like CMRR avoided Iref CMRR=common mode reject ratio Derivation of Optimization Equations Derive Vos to compensate for mismatch: +

29. Method of Moments formula is applied this formula: Pi=parameters to be matched • Correlations are considered through second term in the sum Consideration of Correlations Between Parameters • First order Taylor series taken around nominal bias point • Effect of each parameter on the variance of a function of these parameters is individually added by first term in the sum C. J. Abel, C. Michael, M. Ismail, C.S. Teng and R. Lahri, “Characterization of Transistor Mismatch for Statistical CAD of Submicron CMOS Analog Circuits,” ISCAS, 1993

30. Critical Analysis of Electrical-Empirical Parameter-based Mismatch Modeling +Suitable for back-of-the-envelope calculations +Used when starting a design -Usually used to acquire a worst-case estimation -Real results are seldom worst-case, but occur according to a non-uniform probability distribution -No layoutconsideration

31. Outline -Mismatch at transistor, circuit and VLSI levels -Modeling Challenges and Requirements in Deep Sub-Micron -Optimizations to Avoid Mismatch -Past and Present Mismatch Modeling Approaches: -Electrical & Empirical Models -Layout-based Models -BSIM-based Models -Physics-based Models -Insights for Future Models for Mismatch -Summary & Conclusions

32. Layout Dependent Mismatch Modeling Ap=fitting constant for area • Variance of deviation in a parameter is inversely proportional to the area of the transistors to be matched K. R. Lakshmikumar, R. A. Hadaway, M. A. Copeland, “Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design,” JSSC, 1986

33. Layout Dependent Mismatch Modeling Ap=fitting constant for area, WL Sp=fitting constant for distance D between matched transistors • Variance of deviation in a parameter is inversely proportional to the area of the transistors to be matched • Variance of deviation in a parameter is directly proportional to the squared distance between the transistors to be matched • A consequent design strategy is laying out matched pairs closer and selecting their areas as large as possible K. R. Lakshmikumar, R. A. Hadaway, M. A. Copeland, “Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design,” JSSC, 1986 J. M. Pelgrom, C. J. Duinmaijer and P. G. Welbers, “Matching Properties of MOS Transistors,” JSSC, 1989

34. Change in parameter P is modeled as a function of systematic and local variations • Function f is obtained by fitting regression curves on factory provided manufacturing data Extending Distance Parameter in the Fitting Model • Distance parameter in Pelgrom’s model extended to a polynomial model by including first order terms => higher accuracy x,y is location on wafer a,b,c,d fitting constants G. Tulunay, G. Dundar and A. Ataman “A New Approach to Modeling Statistical Variations in MOS Transistors,” ISCAS, 2002

35. Parameters (x,y) formulated using integration over pairs’ areas • A covariance matrix for (x,y) is formulated using Gaussians as an autocorrelation function • Levenberg-Marquardt least squared method used to fit parameters in the formulations to on-chip measurement data Improved Stochastic Estimation • Extensions to include inter-digitated and cross-coupled geometries through usage of stochastic theory y M1 M2 M1 and M2 are matched transistors in common-centroid layout style x M. Conti, P. Crippa, S. Orcioni and C. Turchetti, “Layout-Based Statistical Modeling for the Prediction of the Matching Properties of MOS Transistors,” IEEE TCAS-I, 2002

36. Incorporation of Effective Lengths • Equal nominal mask areas for differing transistor shapes may result in mismatch when lengths in real chip are considered • If L is nominal, L-L is the effective length caused by penetration of doping under channel region L Leffective • Algebraic estimation of L is possible using SPICE models • Pelgrom’s equation used with effective lengths of transistors • Suggestion of usage of effective width and lengths instead, as dotted effective area important for matching M1 M2 equal initial areas for MOS channels (solid lines) transistor channels S. J. Lovett, M. Welten and B. Mason “Optimizing MOS Transistor Mismatch,” JSSC, 1998

37. Higher Regression Order for Area Term • Higher order regression using Cnm terms as fitting constants Cnm : fitting constants • Builds on previous work and uses effective lengths in denominator • The choice of maximum regression order is questionable T. Serrano-Gotarredona and B. Linares-Barranco, “Systematic Width and Length Dependent CMOS Transistor Mismatch Characterization and Simulation,” Analog IC and Signal Processing, 1999

38. Criticism of Layout Dependent Mismatch Modeling All models based on improving Pelgrom’s Equation: +Practical for an initial estimate -Pelgrom’s model loses accuracy for longer distances -More accurate ones requires a costly extraction procedure of fitting constants from the process

39. Outline -Mismatch at transistor, circuit and VLSI levels -Modeling Challenges and Requirements in Deep Sub-Micron -Optimizations to Avoid Mismatch -Past and Present Mismatch Modeling Approaches: -Electrical & Empirical Models -Layout-based Models -BSIM-based Models -Physics-based Models -Insights for Future Models for Mismatch -Summary & Conclusions

40. ij : standard deviation between Pi and Pj Pi : a parameter of i’th transistor Ri : independent N(0,1) random numbers AMI : coefficients of the random numbers -space for parameter P : R3 • Distances represent variances in -space analysis : A33 P3 |13| |23| P2 |12| DMN : distance between transistors sp : fitting constant P1 A32 A22 R2 • Once P1 is fixed to origin, location of other transistors are found using geometry, then Aij values can be extracted on the axes • -space analysis relates variances in parameters to distances between transistors thus preserving space correlations Statistical Mismatch Modeling • Model for space dependent mismatch: C. Michael and M. Ismail, “Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits,” JSSC, 1992

41. Principal Component Analysis (PCA) for Preserving Correlations • Find correlations • Apply PCA by finding eigenvalues and eigenvectors of C first C : principal component vector  : diagonal eigenvalue matrix U : eigenvector matrix P` : normalizedparameter matrix • Normalize each parameter P,Q : parameters P` : normalized parameter • PCA helps preserve parameter correlations by writing each parameter as a function of independent principal components C. Michael and M. Ismail, “Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits,” JSSC, 1992

42. An Example of PCA Application • PCA helps formulate normalized parameters in terms of independent principal components: VFB` : normalized flat-band voltage MUZ` : normalized zero bulk bias mobility Ci : principal components, chosen unit normal • Area relationship is obtained through using a fitting constant • P` values are unit normal, they are used in -space analysis as random numbers so that parameters correlations are preserved • Remember that -space preserved distance based correlations C. Michael and M. Ismail, “Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits,” JSSC, 1992

43. An Approach for SPICE Implementation • SPICE parameters are perturbed directly: x1, x2 : unit normal random numbers r : correlation constant delvt=deviation in threshold voltage delu0=deviation in mobility • Unit normal random numbers, x1 and x2, generated • SPICE parameters, delvt and delu0, are perturbed using different x1 and x2 each time to simulate a new process Q. Zhang, J. J. Liou, J. R. McMacken, J. Thomson and P. Layman, “SPICE Modeling and Quick Estimation of MOSFET Mismatch Based on BSIM3 Model and Parametric Tests,” JSSC, 2001

44. Criticism of BSIM-based Mismatch Modeling +Considers layout +Considers correlations -Correlation constants are somewhat inaccurate themselves -Requires fitting and process related constants -Does not provide an intuitive understanding of mismatch -Parameter inaccuracies due to extraction from wafer may be magnified through PCA

45. Outline -Mismatch at transistor, circuit and VLSI levels -Modeling Challenges and Requirements in Deep Sub-Micron -Optimizations to Avoid Mismatch -Past and Present Mismatch Modeling Approaches: -Electrical & Empirical Models -Layout-based Models -BSIM-based Models -Physics-based Models -Insights for Future Models for Mismatch -Summary & Conclusions

46. Physics-based Mismatch Modeling • Basic idea : Mismatch is a physical phenomenon and physical parameters are independent • Variance in electrical parameters written in terms of geometry dependent variances of physical parameters e : electrical parameter p : physical parameter • pi’s are dependant on size and distance of transistors • pi’s can be Vfb, Tox, W, L, 0, Nsub, etc. • If enumeration factors are such that |e| > |i|, estimation of physical parameter variances from electrical measurements is also possible • Due to complex formulas, CAD tools required P. G. Drennan and C. C. McAndrew, “Understanding MOSFET Mismatch for Analog Design,” JSSC, 2003

47. An Tractable Physics-based Mismatch Model • Random effects mimicked through assigning pdf’s to Level0 parameters Independent Normal W L NSUB VFB n tox Level0 Correlated? pdf? Level1 Cox Vth Correlated? pdf? Level2 k Each node is a parameter Correlated? pdf? Graph structured using SPICE formula hierarchy Level3 ID Correlated? pdf? gm Level4 R. O. Topaloglu and A. Orailoglu, “Mismatch in the Deep Sub-Micron Era : From Physics to Circuits,” ASP-DAC, 2004

48. SVth= SVth * SPHI + SVth * (SVT0 + SVT0* SPHI) NSUB PHI NSUB VT0 NSUB PHI NSUB • Proposed approach provides a manually tractable estimation Connectivity Based Traversal • Chain rule used to relate a high level parameter to physical ones L0 : level 0 L0 NSUB L1 VT0=f1(NSUB) PHI L2 VT0=f2(PHI,NSUB) VT0 Vth=f3(PHI,VT0) Vth L3 R. O. Topaloglu and A. Orailoglu, “Mismatch in the Deep Sub-Micron Era : From Physics to Circuits,” ASP-DAC, 2004

49. SVth= SVth * SPHI + SVth * (SVT0 + SVT0* SPHI) NSUB PHI NSUB VT0 NSUB PHI NSUB • Proposed approach provides a manually tractable solution Connectivity Based Traversal • Chain rule used to relate a high level parameter to physical ones L0 NSUB L1 VT0=f1(NSUB) PHI L2 VT0=f2(PHI,NSUB) VT0 Vth=f3(PHI,VT0) Vth L3 R. O. Topaloglu and A. Orailoglu, “Mismatch in the Deep Sub-Micron Era : From Physics to Circuits,” ASP-DAC, 2004

50. SVth= SVth * SPHI + SVth * (SVT0 + SVT0* SPHI) NSUB PHI NSUB VT0 NSUB PHI NSUB • Proposed approach provides a manually tractable solution Connectivity Based Traversal • Chain rule used to relate a high level parameter to physical ones L0 NSUB L1 VT0=f1(NSUB) PHI L2 VT0=f2(PHI,NSUB) VT0 Vth=f3(PHI,VT0) Vth L3 R. O. Topaloglu and A. Orailoglu, “Mismatch in the Deep Sub-Micron Era : From Physics to Circuits,” ASP-DAC, 2004