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Overview

Overview. Assignment 4: hints Memory management Assignment 3: solution. A4 Ex.1 – Loading Page Tables. The whole page table is copied to the hardware when the process is scheduled Advantage? Disadvantage? Compute the fraction of the CPU time devoted to loading the page tables

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Overview

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  1. Overview • Assignment 4: hints • Memory management • Assignment 3: solution

  2. A4 Ex.1 – Loading Page Tables • The whole page table is copied to the hardware when the process is scheduled • Advantage? • Disadvantage? • Compute the fraction of the CPU time devoted to loading the page tables • 32-bit address space, 8 KB pages • 1 word / 100ns • each process runs for 100 msec

  3. Ex.2 – Using TLBs • A computer keeps its page tables in memory and uses a small TLB • System parameters: • 32 TLB entries • TLB lookup time  10 nsec • page table lookup  50 nsec • What hit rate is needed to have a mean access time of 20 nsec?

  4. Ex.2 – Using TLBs (cont) • Page table entry (Virtual Address, Physical Page Frame) • In a multi-process system • two different page frames may be mapped to the same virtual address of two processes • how do you store this info in the TLB? • How does a TLB function in a system with multiple processes?

  5. Ex.3 – Memory Size • The time to execute an instruction is • 1 µsec • 2001 µsec if a page fault occurs • A program has • 15.000 page faults • an execution time of 60 sec • We double the memory size • the interval between the page faults is doubled • Is now the program twice as fast as before?

  6. Ex.5 – The Aging Algorithm • Reference bit for every page • Shift age-counter right (1 bit) • Copy reference bit as the left-most bit of the age-counter • Which page do we swap out on a fault? Ref. MSB LSB Age-counter

  7. Ex.5 – The Aging Algorithm (cont) • Problems with this algorithm? • Hint 1: We record only one bit per interval and the algorithm’s tick interval is different than the system clock tick. • Hint 2: The counters have a finite number of bits.

  8. Ex.6 – Virtual Address Translation Offset Global table Middle table TLB TLB hit TLB miss swapped? CR3 (reg) • Page Frame on disk: • Free space (RAM) • No space  Swap out • PT lookup: • PT in memory • PT on disk

  9. Ex.6 – Program Run Time • Application • TLB hit rate is 75% • number of memory access is 55.500.000 • Page fault rate 0.005 • System performance for this application • average PT access time is 130 nsec • average DRAM access time is 50 nsec • average disk access time is 9 msec • Which is the application run time • on this system? • on a system with a faster disk with an access time of 6 msec?

  10. Overview • Assignment 4: hints • Memory management • Assignment 3: solution

  11. A3 Ex.1 – 64-bit addressing – Size • the size of the addressable memory in bytes • the number of 100GB disks to store the whole address space (Seagate in 1 year 7.4*10^15B) • the time to read the whole memory with a transfer rate of 1GB/s

  12. Ex.1 – Page Table Size • the size of a simple linear page table with the following page sizes: 4KB, 128KB and 4MBA minimal table line is composed of: • the real page address (64 – offset bits) • present flag (1 bit) • protection flags (3 bits) • modified flag (1 bit) • referenced flag (1 bit) • cache disable flag (1 bit)

  13. Ex.1 – Page Table Size (cont) • 4KB pages (12 bits for the offset) • an address is composed of 52 bits for the page address and 12 for the offset • we have 252 pages • each page table entry is 52 + 7 = 59 bits (7.3 bytes, 8 bytes because of alignment) • page table size = 252 · 8 = 32768 TB • 128KB pages (17 bits for the offset) • page table size = 247 · 7 = 896 TB • 4MB pages (22 bits for the offset) • page table size = 242 · 7 = 28 TB

  14. Ex.2 Inverted Tables • Two different virtual pages of the same process may be mapped to the same physical page • Two equal virtual addresses of different processes may be mapped to the same physical page • Store (PID, Virtual Address) • Avoid collisions: use also process page tables, link related entries, use clever hash functions

  15. Ex.3 – IA-64 • Which is the idea behind region registers?The first three bits of an address corresponds to a register which specifies which memory region has to be used. Each 24 bit register can address 224 regions and in this way the range of possible addresses is increased to 85 bits (61 bits for each region).Regions allows an efficient management of processes (heavy-weight) for multi-tasking environments. • What does pinning mean? Why and where is it used?Pinning is used to mark a page as non-swappable. For example to keep kernel pages in memory.

  16. Ex.3 – IA-64 • Which page sizes are supported? Which size would you choose for stack, heap, mapped I/O and video frame buffer?Supported sizes: 4KB, 8KB, 16KB, 64KB, 256KB, 1MB, 4MB, 16MB, 64MB, 256MB, 4GB • stack: as small as possible (4KB) • heap: depending on system constraints • mapped I/O: device matching size (usually 4KB – 16KB) • video-buffer: 4MB or 16MB • Which TLBs are implemented?Instruction (ITLB) and data (DTLB) • Which are the allowed operations on TLBs?Loading, unloading and pinning

  17. Ex.3 – IA-64 • Which access rights are supported?Write disable, read disable, execute disable and domain • What is a virtual hash page table (VHPT)? How can this be used?The VHPT is an hash table to map addresses. It is implemented in software and is used as an extension of the TLB hierarchy to speed up an address lookup.

  18. Ex.3 – IA-64 • What is virtual aliasing? How and where is this harmful?We have virtual aliasing when more than one virtual page is mapped to the same physical page.On some Itanium models the performance can be degraded when the distance between virtual aliases is less than 1 MB.

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