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E-Voting Machine

E-Voting Machine. Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober. Mon, Nov 3 Layout, Layout, Layout. Secure Electronic Voting Terminal. Status. FSMs are not complete (3/4 done) Layout finished for COMMs block but not globally connected

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E-Voting Machine

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  1. E-Voting Machine • Group M1 • Bohyun Jessica Kim • Jonathan Chiang • Chi Ho Yoon • Donald Cober Mon, Nov 3 Layout, Layout, Layout Secure Electronic Voting Terminal

  2. Status • FSMs are not complete (3/4 done) • Layout finished for COMMs block but not globally connected • SRAMs and row decoders finished • Transistors: LVS:6652 640:Analog Sim Layout:6964 0 8878

  3. Components FF 8 bit (2) FF_C 16 bit (1) XOR 8 bit (4) Inv (1) FA 8bit (4) FA 16 bit (1) FA shift 4/5 bit (4) 8 bit 2:1 MUX(4) COMMS Full Schematic

  4. COMMS Layout Status Update • Layout finished and LVS’ed for both 8-bit encryption parts • Layout finished for 16-bit sum generator (16 bit adder + flip-flop) • Need to do global routing to hook up all 8-bit and16-bit parts • Size got a little bigger (before: 66 by 80, now: 77 by 80) – because of added functions (FF that clears, muxes, etc) • Roadblock • 2:1 8-bit MUX layout: Very difficult to wire I/O from covered M1, hard to pull contact. Already tried multiple versions of 1 bit cell MUX.

  5. Revisit MUXES Old New Preserves 5.7150 height . Eliminates metal 2 interconnect A lot easier for routing Problem: Minimum contact to P-well diffusion of 8-bit flip flop spacing 0.45 is violated with new design.

  6. Components FF 8 bit (2) XOR 8 bit (4) Inv (1) FA 8bit (4) FA shift 4/5 bit (4) 8 bit 2:1 MUX(4) Comms 8-bit Cipher Encryption Schematics LVS: Partition LVS into 8-bit and 16-bit segments

  7. Comms 8-bit Layout

  8. Comms 8-bit Layout Instances / M3+M4

  9. Comms 16-bit Layout

  10. Comms 16-bit Layout Instances / M3

  11. After global wiring within COMMS blockit will look like a square

  12. FSM Layout Status Update • Registers are complete, LVSing and simulating • Floorplan of the FSMs are complete • Layout of Random Logic in the FSMs has not been started • FSM supporting blocks (message rom, user input reg, etc ) have not been started

  13. FSM Floorplan

  14. FSM Floorplan

  15. FSM Floorplan

  16. SRAM Layout Status Update • Row decoders are complete and LVSing • Cell Matrix has been confirmed • SRAM layout is known

  17. SRAM Decoder Layout

  18. SRAM Matrix Layout

  19. SRAM and Decoder Layout

  20. Floorplan Old vs New

  21. TODO: • For Wednesday: Complete final floorplan • Complete FSMs (LVS) • Complete COMMs • For Monday: Complete Global interconnects • Complete connection blocks

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