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E-Voting Machine - Design Presentation

E-Voting Machine - Design Presentation. Group M1 Bohyun Jessica Kim Jonathan Chiang Chi Ho Yoon Donald Cober. Monday Oct 20 th Gate level Schematics CommsBlock Update and Schematics SRAM cell schematic and layout Updated Transistor Count. Secure Electronic Voting Terminal.

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E-Voting Machine - Design Presentation

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  1. E-Voting Machine - Design Presentation • Group M1 • Bohyun Jessica Kim • Jonathan Chiang • Chi Ho Yoon • Donald Cober Monday Oct 20th Gate level Schematics CommsBlock Update and Schematics SRAM cell schematic and layout Updated Transistor Count Secure Electronic Voting Terminal

  2. Status Update • Updated Transistor Counts • Structural Verilog Entire System • Gate-level Schematics (Comms + SRAM) • Simulation of Individual Blocks and Whole System • Gate-level Layout • Refining Floorplan Immediate Issues • Issue with Analog Simulation

  3. constant init Data Bus Card Reader 0 1 Machine Init FSM 8 bit MUX Encryption Key SRAM Key Register 8 bit Add/Sub Fingerprint Scanner 8-bit REG User ID SRAM User ID FSM T: 88 Selection Counter T: 128 0 1 0 1 0 1 8 bit MUX 8 bit MUX 8 bit MUX Write-in SRAM User Input 8 bit FullAdder 8 bit FullAdder 8 bit FullAdder Selection FSM Choice SRAM TX_Check XOR COMMS Register XOR Confirmation FSM Message ROM 8 bit FullAdder Display Shift Register In Shift Register Out 8-bit REG

  4. SRAM Resized Schematics Redone Layout 32 bit by 8 bit Array Layout Next time: Simulation

  5. SRAM Single Cell Resized Schematic

  6. SRAM Single Cell Layout Last Time Updated Layout (4.095 X 2.97)

  7. SRAM 32 by 8 Bit Cell Layout Dimensions: 131.76 by 18.72 Dimensions: 131.76 by 18.72

  8. SRAM cont’d (decoder) Full Adder 1bit

  9. COMMS Redesigned Implementation Walkthrough Full schematics and gate level blocks Basic adder and xor layouts Next time: Simulation

  10. COMMS BLOCK Hardware Implementation 1 StatesinA[7:0]inB[7:0]sel_outsel_shift[1:0]sel_sumv_out[7:0] (1) delta sum[7:0] 0 00 0 v_out0 = sum[7:0] (2) v1 sum[7:0] 0 01 1 v_out1= (C+D) (3) v1 << 4 k0 1 10 0 v_out2= (A+B) ^ (C+D) (4) v1 >> 5 k1 1 11 0 v_out3 = (A+B) ^ (C+D) ^ (E+F) (5) v0 out3 0 1 1 v_outx = V0 + (A+B) ^ (C+D) ^ (E+F) States (6)-(9) same as above except using k2, k3, and flip v1, v0 Implementation goes through 9 states/clk cycles each iteration to update output function v_outx. Reusing of: (1x) 8 bit Full adder/sub (Ripple carry) [16*8 = 128] (2x) 2:1 8 bit MUX for output pass-through [4*8*2 = 64] (8x) 2-input XORS [6*8 = 48] (1x) 8 bit REG [11*8 = 88] (1x) 4:1 8 bit MUX for shifting selection [12*8 = 96] In addition, logic will to iterate 8 times and be controlled via FSM machine that uses: (2x) 3:1 8 bit MUX for state input selection [8*8*2 = 128] (2x) 1 bit Counter adder for updating cycle [16*2 = 32] (2x) 1 bit REG for storing updated cycle [11*2 = 22] Total: 606 Advantages: Saves transistors and area for Comms Block Disadvantages: Very heavy pass-logic from MUX layers and XOR High clk frequency required since reusing same components for calculating outx by stages. This translates to higher power consumption since we are trying to do more with less hardware. Tradeoff: Every 8-bit MUX uses 4*8 = 32 transistors compared to 8-bit Full Adder 16*8 = 128 transistors. However MUXES have high pass-logic so area vs. power tradeoff is concerned here. 3:1 8 bit MUX 3:1 8 bit MUX inA[7:0] inB[7:0] sel_shift[1:0] Logical Shifter Code 0 1 sel_sum inA[7:0]sel_shift[1:0] delta 00 v1 01 v1 << 4 10 v1 >> 5 11 8 bit MUX 00 01 10 11 T: 32 4:1 8 bit MUX T: 64 8’h00 8 bit FullAdder/Sub 0 1 sel_out 8 bit MUX T: 128 T: 32 1 bit FullAdder XOR T: 48 1-bit REG clk 8-bit REG clk T: 88 v_outx sum += delta; v0 += ((v1<<4)+k0) ^ (v1+sum) ^ ((v1>>5)+k1); v1 += ((v0<<4)+k2) ^ (v0+sum) ^ ((v0>>5)+k3);

  11. COMMS BLOCK Hardware Implementation 2 sum delta 0 1 sel_outoutput 0 pass sum, V1 1 pass new sum, V0 16 bit MUX 16 bit Add/Sub Implementation 2 does concurrent calculations for all 3 parts of function, completes full iteration of calculations in 2 clk cycles. Uses: (1x) 8 bit Full adder/sub (Ripple carry) [16*8 = 128] (3x) 8 bit Full adder (Ripple carry) [12*8*4 = 384] (4x) 2:1 8 bit MUX for output pass-through [4*8*4 = 128] (16x) 2-input XORS [6*16 = 96] (2x) 8 bit REG [11*8*2 = 176] (1x) 1 bit Counter adder for updating cycle [16] (1x) 1 bit REG for storing updated cycle [11] Total: 939 In addition, logic will not need complex FSM, just needs to do 8 iterations using 16 cycles. Advantages: Low pass logic, speed performance, low power, MUX logic transistor count essentially halved. Disadvantages: More Transistor Count and larger area. Tradeoff: Larger area but low pass logic from reduced MUX and complex FSM simplifies design, increases speed and minimizes power. 16-bit REG V1 K0 V1 clk V1 K1 V0 T: 88 T: 128 0 1 0 1 0 1 8 bit MUX 8 bit MUX 8 bit MUX T: 32 T: 32 T: 32 sel_out {V1[3:0], 4’b0} {5’b0, V1[7:5]} 8 bit FullAdder 8 bit FullAdder 8 bit FullAdder T: 128 T: 128 T: 128 XOR 1 bit FullAdder XOR 1-bit REG 8 bit FullAdder T: 128 clk 8-bit REG clk T: 88 sum += delta; v0 += ((v1<<4)+k0) ^ (v1+sum) ^ ((v1>>5)+k1); v1 += ((v0<<4)+k2) ^ (v0+sum) ^ ((v0>>5)+k3); v_outx

  12. COMMS BLOCK Hardware Implementation 3 V0_in V1_in K0 K1 K2 K3 FFC V1_in V0_in Advantages: Lowest pass logic, speed performance, low power, MUX logic transistor count halved. Disadvantages: Double Transistor Count and larger area. Tradeoff: Larger area but low pass logic from reduced MUX, no FSM simplifies design, and 1 cycle per computation increases speed and minimizes power by factor of 2. 1 cycle for calculating: sum += delta; v0 += ((v1<<4)+k0) ^ (v1+sum) ^ ((v1>>5)+k1); v1 += ((v0<<4)+k2) ^ (v0+sum) ^ ((v0>>5)+k3); V0_out V1_out

  13. COMMS Full Schematic Advantages: Low pass logic, speed performance, low power, MUX logic transistor count essentially halved. Disadvantages: More Transistor Count and larger area. Tradeoff: Larger area but low pass logic from reduced MUX and complex FSM simplifies design, increases speed and minimizes power.

  14. COMMS cont’d (smaller blocks) Full Adder 8bit Full Adder 1bit

  15. COMMS cont’d (smaller blocks) Full Adder 16 bit FF 8 bit

  16. COMMS cont’d (smaller blocks) Full Adder << 4 bits Full Adder >> 5 bits

  17. COMMS cont’d (smaller blocks) FF 16 bit XOR 8 bit

  18. COMMS cont’d (smaller blocks) FF 16 bit XOR 8 bit

  19. COMMS cont’d (smaller blocks) XOR 1 bit

  20. Full adder 1-bit layout

  21. XOR 1-bit layout

  22. Comms Block Structural Verilog `include "gatelib.v" // Top level CommsBlock with clocking module CommsBlock_Comb(V0_out, V1_out, V0_reg, V1_reg, a1_out, a1_out_8bit, a1_mux, a1_in, x1, x2, x3, x4, f1, f2, f3, f4, f5, f6, v1_sl, v1_sr, v0_sl, v0_sr, arr_V, arr_K, V0_sel, V1_sel, sum_clr, en_de, clk); output [7:0] V0_out, V1_out, V0_reg, V1_reg; output [7:0] a1_out_8bit, v1_sl, v1_sr, v0_sl, v0_sr, x1, x2, x3, x4, f1, f2, f3, f4, f5, f6; output [15:0] a1_out, a1_in, a1_mux; input [15:0] arr_V; input [31:0] arr_K; input sum_clr, V0_sel, V1_sel, en_de, clk; //Set to 0 for encryption, 1 for decryption wire [7:0] V0_add, V1_add, a1_out_8bit, V0_reg, V1_reg, V0_in, V1_in, K0, K1, K2, K3, v1_sl, v1_sr, v0_s1, v0_sr, f1, f2, f3, f4, f5, f6, x1, x2, x3, x4; wire [15:0] delta, a1_out, a1_in; assign K0 = arr_K[31:24]; assign K1 = arr_K[23:16]; assign K2 = arr_K[15:8]; assign K3 = arr_K[7:0]; assign delta = 16'b0000101000000000; //0x0A00 assign v1_sl = {V1_in[3:0], 4'b0}; assign v1_sr = {5'b0, V1_in[7:5]}; assign v0_sl = {V0_in[3:0], 4'b0}; assign v0_sr = {5'b0, V0_in[7:5]}; assign a1_out_8bit = a1_out[7:0]; DFF_C regSum[15:0](a1_out, a1_in, sum_clr, clk_not); DFF regV0[7:0](V0_reg, V0_out, clk_not); DFF regV1[7:0](V1_reg, V1_out, clk); mux21_8bit mux81(V1_in, V0_sel, arr_V[7:0], V1_reg), mux82(V0_in, V1_sel, arr_V[15:8], V0_reg), mux83(V0_add, V0_sel, arr_V[15:8], V0_reg), mux84(V1_add, V0_sel, arr_V[7:0], V1_reg); add_16 a161(a1_in, Co_a1, a1_out, delta, en_de); add_8 a81(f1, Co_f1, K0, v1_sl, en_de), a82(f2, Co_f2, a1_out_8bit, V1_in, en_de), a83(f3, Co_f3, v1_sr, K1, en_de), a84(f4, Co_f4, K2, v0_sl, en_de), a85(f5, Co_f5, a1_out_8bit, V0_in, en_de), a86(f6, Co_f6, v0_sr, K3, en_de), a87(V0_out, Co_V0_out, V0_add, x2, en_de), a88(V1_out, Co_V1_out, V1_add, x4, en_de); xor_8 xor_1(x1, f1, f2), xor_2(x2, x1, f3), xor_3(x3, f4, f5), xor_4(x4, x3, f6); INV inv1(clk_not, clk); endmodule

  23. Comms Block Structural Verilog //2:1 8-bit MUX module mux21_8bit(S, sel, A, B); output [7:0] S; input [7:0] A, B; input sel; MUX2 m0(S[0], sel, A[0], B[0]), m1(S[1], sel, A[1], B[1]), m2(S[2], sel, A[2], B[2]), m3(S[3], sel, A[3], B[3]), m4(S[4], sel, A[4], B[4]), m5(S[5], sel, A[5], B[5]), m6(S[6], sel, A[6], B[6]), m7(S[7], sel, A[7], B[7]); endmodule //Standard 16-bit full-adder, ripple carry module add_16(S, Co, A, B, Ci); input [15:0] A, B; input Ci; output [15:0] S; output Co; fa1bit a1(S[0], C1, A[0], B[0], Ci), a2(S[1], C2, A[1], B[1], C1), a3(S[2], C3, A[2], B[2], C2), a4(S[3], C4, A[3], B[3], C3), a5(S[4], C5, A[4], B[4], C4), a6(S[5], C6, A[5], B[5], C5), a7(S[6], C7, A[6], B[6], C6), a8(S[7], C8, A[7], B[7], C7), a9(S[8], C9, A[8], B[8], C8), a10(S[9], C10, A[9], B[9], C9), a11(S[10], C11, A[10], B[10], C10), a12(S[11], C12, A[11], B[11], C11), a13(S[12], C13, A[12], B[12], C12), a14(S[13], C14, A[13], B[13], C13), a15(S[14], C15, A[14], B[14], C14), a16(S[15], Co, A[15], B[15], C15); endmodule //Standard 8-bit full-adder, ripple carry module add_8(S, Co, A, B, Ci); input [7:0] A, B; input Ci; output [7:0] S; output Co; fa1bit a1(S[0], C1, A[0], B[0], Ci), a2(S[1], C2, A[1], B[1], C1), a3(S[2], C3, A[2], B[2], C2), a4(S[3], C4, A[3], B[3], C3), a5(S[4], C5, A[4], B[4], C4), a6(S[5], C6, A[5], B[5], C5), a7(S[6], C7, A[6], B[6], C6), a8(S[7], Co, A[7], B[7], C7); endmodule //Standard full-adder, has Cin. module fa1bit(SumDiffOut, Cout, Ain, Bin, Cin); output SumDiffOut, Cout; input Ain, Bin, Cin; XOR2 xor1(x1, Ain, Bin), xor2(SumDiffOut, x1, Cin); NAND2 nand1(na1, Ain, Bin), nand2(na2, x1, Cin), nand3(Cout, na1, na2); endmodule

  24. Comms Block Structural Verilog //8 bit XOR module xor_8(Out, A, B); output [7:0] Out; input [7:0] A, B; XOR2 xor1(Out[0], A[0], B[0]), xor2(Out[1], A[1], B[1]), xor3(Out[2], A[2], B[2]), xor4(Out[3], A[3], B[3]), xor5(Out[4], A[4], B[4]), xor6(Out[5], A[5], B[5]), xor7(Out[6], A[6], B[6]), xor8(Out[7], A[7], B[7]); endmodule //Test for Tiny Encryption Algorithm and Comms Block module test_CommsBlock; wire [7:0] V0_out, V1_out, V0_reg, V1_reg, a1_out_8bit, x1, x2, x3, x4, f1, f2, f3, f4, f5, f6, v1_sl, v1_sr, v0_sl, v0_sr; wire [15:0] a1_out, a1_in, a1_mux; reg [15:0] arr_V; reg [31:0] arr_K; reg V0_sel, V1_sel, sum_clr, en_de, clk; CommsBlock_CombmyCommsComb(V0_out, V1_out, V0_reg, V1_reg, a1_out, a1_out_8bit, a1_mux, a1_in, x1, x2, x3, x4, f1, f2, f3, f4, f5, f6, v1_sl, v1_sr, v0_sl, v0_sr, arr_V, arr_K, V0_sel, V1_sel, sum_clr, en_de, clk); always #80 clk = ~clk; initial begin $monitor($time, " V0_out=%h, V1_out=%h, V0_reg=%h, V1_reg=%h, a1_out=%h, a1_in=%h, arr_V=%h, arr_K=%h, V0_sel=%h, V1_sel=%h, sum_clr=%h, clk=%h", V0_out, V1_out, V0_reg, V1_reg, a1_out, a1_in, arr_V, arr_K, V0_sel, V1_sel, sum_clr, clk); clk = 0; sum_clr = 1; en_de = 0; arr_V = 16'h0; arr_K = 32'h0; #80 sum_clr = 0; #83 arr_V = 16'h1234; arr_K = 32'h778cae38; en_de = 0; // en_de: 0 = encrypt enable, 1 = decrypt enable V1_sel = 0; V0_sel = 0; #160 //#323, NegClk, V0_reg stabilizes, refeed to get V1_reg V1_sel = 1; #80 //#403, Pos Clk, V1_reg stabilizes V0_sel = 1; #1200 // Repeat and go through 8 rounds of cycle time $stop; end endmodule

  25. Behavioral Simulation 0 V_temp=xx, V0=xx, V1=xx, sum=xxxx, tranmit_sig=x, decrypt_out=x, arr_V=0000, arr_K=00000000, receive_sig=0, encrypt_in_reg=0, clk=0 3 V_temp=xx, V0=xx, V1=xx, sum=xxxx, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=0, clk=0 8 V_temp=xx, V0=xx, V1=xx, sum=xxxx, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=0 20 V_temp=xx, V0=12, V1=34, sum=0a00, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=1 25 V_temp=xx, V0=20, V1=34, sum=0a00, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=1 35 V_temp=xx, V0=20, V1=eb, sum=1400, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=1 40 V_temp=xx, V0=7f, V1=eb, sum=1400, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=0 50 V_temp=xx, V0=7f, V1=c5, sum=1e00, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=0 55 V_temp=xx, V0=0f, V1=c5, sum=1e00, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=0 60 V_temp=xx, V0=0f, V1=c5, sum=1e00, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=1 65 V_temp=xx, V0=0f, V1=6e, sum=2800, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=1 70 V_temp=xx, V0=c5, V1=6e, sum=2800, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=1 80 V_temp=xx, V0=c5, V1=73, sum=3200, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=0 85 V_temp=xx, V0=20, V1=73, sum=3200, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=0 95 V_temp=xx, V0=20, V1=2a, sum=3c00, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=0 100 V_temp=xx, V0=d0, V1=2a, sum=3c00, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=1 110 V_temp=xx, V0=d0, V1=6a, sum=4600, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=1 115 V_temp=xx, V0=c2, V1=6a, sum=4600, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=1 120 V_temp=xx, V0=c2, V1=6a, sum=4600, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=0 125 V_temp=xx, V0=c2, V1=9c, sum=5000, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=0 130 V_temp=xx, V0=fd, V1=9c, sum=5000, tranmit_sig=x, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=0 140 V_temp=xx, V0=fd, V1=58, sum=5000, tranmit_sig=1, decrypt_out=x, arr_V=1234, arr_K=778cae38, receive_sig=0, encrypt_in_reg=1, clk=1 Behavioral simulation runs through 8 iterations, bolded in red, starts from Input: 0x1234 and after 8 iterations our encrypted message is 0xfd58

  26. Structural Simulation 0 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=xxxx, a1_in=xxxx, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 3 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=xxxx, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 7 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=xxxX, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 8 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=xxx0, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 9 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=XX00, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 10 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=XX00, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 11 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=0a00, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=1, clk=0 80 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=0a00, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=0, clk=1 160 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0000, a1_in=0a00, arr_V=0000, arr_K=00000000, V0_sel=x, V1_sel=x, sum_clr=0, clk=0 163 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=0a00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 167 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=0000, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 168 V0_out=xx, V1_out=xx, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 178 V0_out=xx, V1_out=xX, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 179 V0_out=xX, V1_out=xX, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 180 V0_out=xX, V1_out=xX, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 181 V0_out=xX, V1_out=x8, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 182 V0_out=XX, V1_out=X8, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 183 V0_out=XX, V1_out=X8, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 184 V0_out=X0, V1_out=18, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 186 V0_out=X0, V1_out=18, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 189 V0_out=20, V1_out=18, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 240 V0_out=20, V1_out=18, V0_reg=xx, V1_reg=xx, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=1 243 V0_out=20, V1_out=18, V0_reg=xx, V1_reg=18, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=1 320 V0_out=20, V1_out=18, V0_reg=xx, V1_reg=18, a1_out=0a00, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=0, sum_clr=0, clk=0 323 V0_out=20, V1_out=18, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1400, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 329 V0_out=20, V1_out=18, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 339 V0_out=20, V1_out=48, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 340 V0_out=20, V1_out=68, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 341 V0_out=20, V1_out=e9, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 342 V0_out=20, V1_out=eb, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=0 400 V0_out=20, V1_out=eb, V0_reg=20, V1_reg=18, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=0, V1_sel=1, sum_clr=0, clk=1 403 V0_out=20, V1_out=eb, V0_reg=20, V1_reg=eb, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 410 V0_out=20, V1_out=4a, V0_reg=20, V1_reg=eb, a1_out=1400, a1_in=1e00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 560 V0_out=de, V1_out=c5, V0_reg=7f, V1_reg=eb, a1_out=1e00, a1_in=2800, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 563 V0_out=de, V1_out=c5, V0_reg=7f, V1_reg=c5, a1_out=1e00, a1_in=2800, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 571 V0_out=de, V1_out=d5, V0_reg=7f, V1_reg=c5, a1_out=1e00, a1_in=2800, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 720 V0_out=9f, V1_out=6e, V0_reg=0f, V1_reg=c5, a1_out=2800, a1_in=3200, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 723 V0_out=9f, V1_out=6e, V0_reg=0f, V1_reg=6e, a1_out=2800, a1_in=3200, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 730 V0_out=9f, V1_out=06, V0_reg=0f, V1_reg=6e, a1_out=2800, a1_in=3200, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1

  27. Structural Simulation 880 V0_out=7b, V1_out=73, V0_reg=c5, V1_reg=6e, a1_out=3200, a1_in=3c00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 883 V0_out=7b, V1_out=73, V0_reg=c5, V1_reg=73, a1_out=3200, a1_in=3c00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 890 V0_out=7b, V1_out=70, V0_reg=c5, V1_reg=73, a1_out=3200, a1_in=3c00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1040 V0_out=7b, V1_out=2a, V0_reg=20, V1_reg=73, a1_out=3c00, a1_in=4600, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1043 V0_out=7b, V1_out=2a, V0_reg=20, V1_reg=2a, a1_out=3c00, a1_in=4600, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1050 V0_out=7b, V1_out=08, V0_reg=20, V1_reg=2a, a1_out=3c00, a1_in=4600, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1200 V0_out=80, V1_out=6a, V0_reg=d0, V1_reg=2a, a1_out=4600, a1_in=5000, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1203 V0_out=80, V1_out=6a, V0_reg=d0, V1_reg=6a, a1_out=4600, a1_in=5000, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1210 V0_out=80, V1_out=2a, V0_reg=d0, V1_reg=6a, a1_out=4600, a1_in=5000, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1360 V0_out=b4, V1_out=9c, V0_reg=c2, V1_reg=6a, a1_out=5000, a1_in=5a00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1363 V0_out=b4, V1_out=9c, V0_reg=c2, V1_reg=9c, a1_out=5000, a1_in=5a00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1370 V0_out=b4, V1_out=8c, V0_reg=c2, V1_reg=9c, a1_out=5000, a1_in=5a00, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1520 V0_out=38, V1_out=58, V0_reg=fd, V1_reg=9c, a1_out=5a00, a1_in=6400, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1523 V0_out=38, V1_out=58, V0_reg=fd, V1_reg=58, a1_out=5a00, a1_in=6400, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 1530 V0_out=38, V1_out=50, V0_reg=fd, V1_reg=58, a1_out=5a00, a1_in=6400, arr_V=1234, arr_K=778cae38, V0_sel=1, V1_sel=1, sum_clr=0, clk=1 Structural simulation terminates after 8 iterations, bolded in red, at 0xfd58 like behavioral. Decryption works in the reverse fashion with adders doing subtraction instead.

  28. FSM Machine Initialization FSM Schematics Next time: Remaining FSM Schematics Simulation

  29. Machine Initialization FSM Schematic #1

  30. Machine Initialization FSM Schematic #2

  31. Changes during structural • FSM Encoding: • FSMs with 6, 12, 7 and 9 states • Binary encoding has about the same transistor count as One-hot encoding • One-hot is much easier to layout • Address Counter • SRAM data is accessed sequentially • Address registers are linked as counters • Counters can increment, decrement, and reset • Requires an additional type of register

  32. COMMS Optimized Gate Schematics Transistor Counts

  33. FSM Verilog Transistor Counts FSM Optimized Gate Schematics Transistor Counts

  34. SRAM & Peripheral Blocks Transistor Counts

  35. Updated Floorplan • The aspect ratio still about 2:1 • Doubled size in COMMS Block • The interconnects travel heavily over the FSM • These are mostly 1 bit enable signals and some are address lines • The address lines and data bus are buffered

  36. Issues Persisting problem with Analog Simulation using SCMOS18 library Next Time Simulation Results All Individual Functional Blocks FSM Gate-level Schematics and Layout Update Global Schematic Routing

  37. Questions? Thank you!

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