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Programming Models and Hardware Dependent Software Abstraction for Multi-Processor SoC

Programming Models and Hardware Dependent Software Abstraction for Multi-Processor SoC. Ahmed A. Jerraya TIMA Laboratory 46 Avenue Felix Viallet, 38031 Grenoble Cedex France Tel: +33 476 57 47 59, Fax: +33 476 47 38 14 Email: Ahmed.Jerraya@imag.fr. CASTNESS'07 Rome, Italy

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Programming Models and Hardware Dependent Software Abstraction for Multi-Processor SoC

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  1. Programming Models and Hardware Dependent Software Abstraction for Multi-Processor SoC Ahmed A. Jerraya TIMA Laboratory 46 Avenue Felix Viallet, 38031 Grenoble Cedex France Tel: +33 476 57 47 59, Fax: +33 476 47 38 14 Email: Ahmed.Jerraya@imag.fr CASTNESS'07 Rome, Italy 15-17 January 2007

  2. TIMA LaboratoryTechniquesof Informaticsand Microelectronicsfor computer Architecture • CNRS – INPG – UJF • ~ 140 persons (incl. CMP) • Research • Concurrent Integrated Systems, M. RENAUDIN • System Level Synthesis, A. JERRAYA, F. PETROT • MiCro & Nano Systems, S. BASROUR & B. COURTOIS • Reliable Mixed-signal Systems, S. MIR • QuaLiFication of Circuits, R. VELAZCO • Verification and Modeling of Digital Systems, D. BORRIONE • Service: CMP • 500 institutions, 60 countries, ICs, MEMS, CAD, Kits • CMOS .12µ ST

  3. CPU IP DSP NoC System-Level Synthesis Group (SLS) • Research area : • System on chip design • Objectives : • Decrease the design time through new design methodologies and tools • Methods : • Theoretical work : • Hardware/software interfaces • Heterogeneous components based design • Applications to understand the needs: Divx, MJPEG, H264 • Validation of research in collaboration with industry MPEG4 Encoder

  4. System-Level Synthesis (SLS) • Staff (25): • Group Leaders: A. Jerraya, F. Pétrot • Permanent Staff : P. Amblard, A. Bouchhima, L. Kriaa F. Rousseau, W. Youssef, N. Zergainoh • Ph.D. students: Y. Atat, Y. Cho, A. Chureau, P. de Massas, P. Gerin, X. Guérin, S. Han, A. Kouadri Mostéfaoui, M. Oyamada, K. Popovici, B. Senouci, H. Shen • Industrial Ph.D.: M. Fiandino, R. Lemaire, Ch. Sahnine • Contracts: • Industrial cooperation • National & EC Funding: MEDEA, IST, RNRT, ITEA

  5. Acknowledgement • Prof F. Pétrot, Dr. F. Rousseau • Dr. A. Bouchhima, Dr W Youssef • PhD Students • A. Chureau • K. Popovici • H. Shen • X. Guérin • P. Gerin

  6. Summary SW IPs SW IP Component (F2, F5) SW IP Component (F4, F6) SW IP Component (F3) SW IP Component (F1) • Context • MPSoC design: • Abstract software (e.g.: CORBA, Simulink µCCM) and heterogeneous hardware (DSP, RISC) • Performance/cost constraints • Time-to-market: • Reuse HW Platforms and SW components • Problems • Architecture exploration for mapping of SW components on Hardware platform • Difficult Hardware dependent Software debug • The Challenge: Fast and efficient mapping of software components to hardware platform Binary SW Application SW DSP #1 HDS C5510 200 Mhz CAN DSP #2 C5510 CNA FPGA 200 Mhz Contrôle du signal radio GPP Bus MPC860 Ethernet 80 Mhz Target Hardware platform Contrôle

  7. Outline 1.- Programming Models: the Bridge between Hardware and Software 2.- Application-Specific Programming Models to Handle MPSoC 3.- Programming Models at Different Abstraction Levels 4.- Next Generation Design Flow Based on Programming Models 5.- Summary

  8. Multi-Thread application SW interface Operating System Specific I/O HW/SW Interface Model HAL CPU MEM DMA bridge Networkinterface Hardware Co-processor HW PROTOCOL Context: Heterogeneous MPSoC Software Node Hardware Node • Heterogeneous MPSoC • Hardware nodes for performance • Software nodes for flexibility • Communication network Communication Network • Software node: • Specific CPU subsystem • GPP, DSP, ASIP, ... • I/O and memory architecture • Layered SW architecture • Application code (threads) • Hardware dependent software A programming model abstracts HW-SW interfaces for SW design.

  9. Programming Model: The Classical Solution to Abstract HW-SW Interfaces SW modules ... • Abstract HW model for SW design • Programming language with implicit primitives (e.g. module hierarchy & threads in SystemC) • API: Application Programming Interface (MPI, Posix Threads) • Simulation model (MPICH, Linux) • Used by SW community to free the SW designer from knowing HW details. • Facilitate porting of application SW over different architectures that support the same API. SW 2 SW 1 SW n API SW modules SW modules API API Execution Environment HW dependent SW (HDS) HW architecture Simulation Implementation

  10. MPEG4 API API CPUy IP1 HDSy Communicationnetwork IP2 IP3 SW Reuse Based on Programming Model (API): SW MPEG4 • Executing same SW on different architectures using different CPUs • HDS = Hardware dependent Software (OS, HAL, Specific I/O) HAL API API CPUx HDSx Comm. network IP

  11. @ data CTRL Start done xy z HW-SW Interfaces CPU Bus HW-Adaptation Defining HW-SW Interfaces Sequential SW program … Call HW (x, y, z) • Application SW Designer: A set of system calls used to hide the underlying execution platform. Also Called Programming Model • HW designer: A set of registers, control signals and more sophisticated adaptors to link CPU to HW subsystems. • System SW designer: Low level SW implementation of the programming Model for a given HW architecture. • CPU is the ultimate HW-SW Interface • Sequential scheme assuming HW is ready to start low level SW design • SoC Designer • Abstracts both HW and SW in addition to CPU • HW-SW interfaces tradeoff API HW Dependant SW CPU (local Architecture) xy z HW function wait start …

  12. Outline 1.- Programming Models: the Bridge between Hardware and Software 2.- Application-Specific Programming Models to Handle MPSoC 3.- Programming Models at Different Abstraction Levels 4.- Next Generation Design Flow Based on Programming Models 5.- Summary

  13. Abstract HW/SW Interface Fully explicit HW/SW Interface Fully implicit HW/SW Interface GAP Software Sub-System Software Thread 1 Software Thread 1 Early HW/SW integration Hardware Classical HW/SW Interfaces Abstraction Models : The GAPS Software Sub-System Binary SW Appli Software Thread 1 Software Thread 2 OS HAL ISS IT Ctrl MEM FIFO Hardware HW Software design Virtual Prototype System Level Partition ning Integration Hardware/Software discontinuity Functional specification ISA/RTL Hardware design Correction cycle

  14. Programming Model RTL (Verilog, BinSW) Virtual Prototype (RTL HW, BinSW, e.g. SystemC) MPI RT-CORBA CORBA SDL HW-SW Interfaces Explicit concepts SW: ALL SW: ALL High Level Synchro- nisation Communi- cation - Concurrency - Threading CPU imple- mentation RTL HW CPU orga- nization HW: NONE HW: NONE HW: NONE Parallel Programming Models: The mixed HW-SW interfaces GAP Distributed SW Design SoC Design Mixed Abstract HW-SW Interfaces models

  15. Transaction Accurate (TLM HW, TLM SW: Abstract CPU+HAL) Virtual Architecture (Abstract HW, HL SW: Threads & Abstract OS +CPU SS) - OS - Specific I/O Communication/ Computation Modules • CPU SS- Abstract Bus • - Explicit HW • modules Abstract Interconnect HDS development platform SW application development platform Parallel Programming Models for MPSoC Distributed SW Design SoC Design Programming Model RTL (Verilog, BinSW) Virtual Prototype (RTL HW, BinSW, e.g. SystemC) MPI RT-CORBA CORBA SDL HW-SW Interfaces Explicit concepts SW: ALL SW: ALL Synchro- nisation Communi- cation - Concurrency - Threading CPU imple- mentation RTL HW CPU orga- nization HW: NONE HW: NONE HW: NONE

  16. Outline 1.- Programming Models: the Bridge between Hardware and Software 2.- Application-Specific Programming Models to Handle MPSoC 3.- Programming Models at Different Abstraction Levels 4.- Next Generation Design Flow Based on Programming Models 5.- Summary

  17. HW modules Application Software + HW modules HW modules Hardware Application software Hardware Dependent SW HW-SW interfaces to be abstracted Boot MemBank CPU API TaskMgr HW platform Abstract SW Execution engine Wires Hardware HW & inf. to CPU or abs. channels Hardware CPU (Mem) Ctrl Hardware interconnects Abstract comm. channels • Traditional view of SoC • CPU is HW-SW interface. • SW validation assumes HW ready. • SoC Model with Abstract HW-SW Interfaces • Separate HW and SW design • Better HW & SW reuse. • HW-SW Interfaces to be abstracted • Require to model HW, SW and CPU • Allow new architecture trade-off. Key Innovation to Higher Level HW/SW Interface Abstraction: from CPU to SW Execution Subsystem

  18. To be abstracted HAL software layer Details of CPU subsystem SW interface : HAL API Context switch Synchronization (e.g. spin lock) IO Read/Write HW interface : HW protocol Bus Protocol,… Specific HW interface (FIFO) HAL API HW/SW Interface At Transaction Accurate Level HW PROTOCOL Interface Modeling at Transaction Accurate Level Multi-Thread application Operating System Specific I/O HAL CPU MEM DMA bridge Networkinterface Hardware Co-processor Hardware

  19. Software Sub-System Software Thread 1 Software Thread 2 SW Hyb HW Hardware Services for HW/SWInterfaces Adaptation • Both HW and SW interfaces are modeled as set of services (provided/required) • Component based interface adaptation • Software elements • Hardware elements • Hybrid elements

  20. High Simulation speed Easiest functional validation No Operating System details No details on communications 6 software and 2 hardware tasks Execution model synchronized with communications Motion JPEG application :System Level Model SOFTWARE IQ ZZ VLD IDCT DEMUX LIBU HARDWARE TRAFFIC GENERATOR VIDEO OUT Communication thread channel

  21. HAL API HW/SW Interface At Transaction Accurate Level HW PROTOCOL Motion JPEG application :Virtual Prototype Model • Software tasks executed on a POSIX compliant OS: MUTEK • Software interpreted by the target processor ISS • Rest of the system at RTL level Binary SW Appli Mutek OS HAL ISS IT Ctrl VCI Cross bar • Detailed communications • Performances precision • Fastidious Operating System validation • Very slow simulation MEM FIFO TG VIDEO

  22. CXT SPIN DIAGNOSTIC OS SMP IT IO_ACCESS INIT LOCK CONSUME INIT THIS READ MASK SWITCH UNLOCK COUNT WRITE UNMASK INTERRUPT SPIN EXEC_UNIT IT_CTRL VCI_WRAPPER MEM Motion JPEG application:Transaction Accurate Model HAL API • Pure software elements • CONTEXT • INTERRUPT • Pure Hardware • VCI FIFO • Hybrid elements • CROSSBAR • VCI WRAPPER • EXEC_UNIT • … CONTEXT XBAR FIFO HW PROTOCOL HS_READ HS_WRITE REQ ACK DATA REQ ACK DATA

  23. SW interface HW/SW Interface At Transaction Accurate Level HW interface SW interface HW/SW Interface At Virtual Architecture Level HW interface Interfaces Modeling at Virtual Architecture Model • Apply the proposed approach to other abstraction level : • Virtual Architecture, abstract the operating system and the specific communication Multi-Thread application Operating System Specific I/O • HW/SW interface design automation to enable : • Architecture exploration. • Refinement HAL CPU MEM DMA bridge Networkinterface Hardware Co-processor Hardware

  24. MJpeg Appli MJpeg Appli MJpeg Appli Same SW Same SW POSIX API POSIX API POSIX API MUTEK OS MUTEK OS Host OS (LINUX) HAL API POSIX API HAL (sparc) T.A. Model Same SW ISS + Sub-System HW PROTOCOL POSIX API HW PROTOCOL SW view of HW Hardware Hardware System Level Transaction Accurate Virtual Prototype 0.017s/frame X 70 1.2s/frame X 200 235s/frame (Fully explicit HW-SW interfaces) (Fully implicit HW-SW interfaces) (Abstract HW-SW interfaces) Experiment Simulations • Same SW application code in the 3 models • 3 simulations • Same OS code in T.A. and V.P.

  25. Outline 1.- Programming Models: the Bridge between Hardware and Software 2.- Application-Specific Programming Models to Handle MPSoC 3.- Programming Models at Different Abstraction Levels 4.- Next Generation Design Flow Based on Programming Models 5.- Summary

  26. HW & SW Design Approaches for SoC HW Design Debug and integration Application SW development Platform (VA) Application SW Design Application SW and HDS Design Debug/ Performances validation HDS development Platform(TA) HW-SW Interfaces design Time saving HW Design HW and SW Design Approaches Time • Classical HW & SW design approaches for computers Application SW Design HW Design HDS Design API SW Debug • Using high level HW-SW Interfaces models

  27. Conclusions: Programming Models for MPSoC • Abstract HW-SW Interfaces to enable Higher than RTL design • A platform for early application SW & HDS validation • Better match between HW & SW • Is an opportunity for new HW-SW codesign approaches and architecture Exploration

  28. Thank You

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