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Status of JPL Usage of Actel RTSX-SU/S FPGAs

Status of JPL Usage of Actel RTSX-SU/S FPGAs. Dr. Douglas Sheldon Section 514 Electronic Parts Engineering. JPL Mission FPGA Utilization Plan. Number of Actel MEC and UMC parts, by project, launching before the end of 2007

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Status of JPL Usage of Actel RTSX-SU/S FPGAs

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  1. Status of JPL Usage of Actel RTSX-SU/S FPGAs Dr. Douglas Sheldon Section 514 Electronic Parts Engineering Douglas Sheldon - JPL

  2. JPL Mission FPGA Utilization Plan • Number of Actel MEC and UMC parts, by project, launching before the end of 2007 • It is assumed that all projects launching in 2008 and beyond will use UMC parts Douglas Sheldon - JPL

  3. Deep Impact - Mission Success Probability for Actel FPGA Fly-by is dual string: 6 months in-flight, Fly-by cameras are single string: <500 hours of operations in space all related assemblies have seen >700 operating hours Impactor and impactor camera are single string: <72 hours of operations in space all related assemblies have seen >700 operating hours Douglas Sheldon - JPL

  4. Deep Impact - FPGA Device Reliability Models, Data and Assumptions • Weibull Distribution Analysis from Industry Tiger Team Data: • Parameter estimation: • Aerospace - Shape factor is estimated as 0.125. Failure rate @ 5,000 hours is 3,642 FITs at 25C • GSFC - Shape factor is estimated as 0.25. Failure rate @ 5,000 hours is 1,623 FITs at 27C • Exponential Distribution Analysis from Mars Exploration Rover flight and surface operations: • Assumptions for exponential distribution are: • Burn-in and/or any pre-screening performed on the MER and DI FPGA parts have eliminated infant mortality. • Constant failure rate for FPGA parts used for MER and DI flight mission. • The impact of different biases and operating temperatures of the MER and DI FPGA parts is minimum. • Parameter estimation: • MER FPGA operational device-hours as of 12/1/04 is estimated as 488,620 dev-hrs. • Upper bound of failure rate at 5,000 hours is 1,883 FITs with 60% confidence level and 4,707 FITs with 90% confidence level. Douglas Sheldon - JPL

  5. FPGA Device Reliability Comparison by Different Models Douglas Sheldon - JPL

  6. FPGA Configuration in DI Douglas Sheldon - JPL

  7. DI Mission Success Probability • DI probability of mission success* during operations is between 94% and 98% from different FPGA device level reliability models. • Based on this analysis, the significant amount of testing conducted by the DI project, and the short mission duration the likelihood of loss of mission due to an FPGA failure is considered low to very low. * Note that DI full mission success does not require full functionality of MRI. Douglas Sheldon - JPL

  8. Summary of JPL DPA’s on Actel FPGA’s Douglas Sheldon - JPL

  9. Bond Pull Data Details Douglas Sheldon - JPL

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