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Chapter 2: Combinational Logic Circuit (Part1)

EET107/3 DIGITAL ELECTRONICS 1. Chapter 2: Combinational Logic Circuit (Part1). Basic Combinational Logic Circuits. AND-OR Logic SOP expression – AND-OR logic AND gate (product term) OR gate (summing all product term)c

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Chapter 2: Combinational Logic Circuit (Part1)

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  1. EET107/3DIGITAL ELECTRONICS 1 Chapter 2: Combinational Logic Circuit (Part1)

  2. Basic Combinational Logic Circuits • AND-OR Logic • SOP expression – AND-OR logic • AND gate (product term) • OR gate (summing all product term)c • AND-OR circuit can have any number of AND gate, with any number of inputs

  3. Basic Combinational Logic Circuits • AND-OR-Invert Logic • When output of AND-OR circuit is complemented • POS expression can implemented with AND-OR invert logic

  4. Basic Combinational Logic Circuits • Exclusive-OR logic • Combination 2 AND gates and 1 OR gate and 2 inverters

  5. Basic Combinational Logic Circuits • Exclusive-NOR logic • Complement of exclusive OR function

  6. Basic Combinational Logic Circuits • Exclusive-NOR Equation

  7. Basic Combinational Logic Circuits • The Universal Property of NAND and NOR Gates

  8. Basic Combinational Logic Circuits • The Universal Property of NAND and NOR Gates

  9. Basic Combinational Logic Circuits • Designing a circuit using only NAND gate • Two kinds of approach • Direct translation – replace the gate other than NAND gate with equivalent NAND • Boolean manipulation – use Boolean theorem to transform the expression into a NAND gate only expression

  10. Basic Combinational Logic Circuits • Designing a circuit using only NAND gate • Direct translation • Assuming you remember the entire equivalent NAND gate • The resulting circuit will consist many NAND gate A B Z C D

  11. Basic Combinational Logic Circuits • Designing a circuit using only NAND gate • (b) Boolean manipulation • No ‘+’ sign • Must have long bar on top • First, obtain Boolean expression for Z A B C D Z

  12. Basic Combinational Logic Circuits • Designing a circuit using only NOR gate • Just like circuit using only NAND gate, there are the same two kinds of approach • Direct translation – replace the gate other than NOR gate with equivalent NOR • Boolean manipulation – use Boolean theorem to transform the expression into a NOR gate only expression

  13. Basic Combinational Logic Circuits • Designing a circuit using only NOR gate • (a) Direct translation

  14. Basic Combinational Logic Circuits • Designing a circuit using only NOR gate • (b) Boolean manipulation • No ‘.’ sign • Must have long bar on top • First, obtain Boolean expression for X

  15. 2.1 Digital Arithmetic Binary arithmetic complement representation complement arithmetic Hexadecimal arithmetic BCD arithmetic Arithmetic circuits Half Adder/Subtractor 4-bit full-adder/subtractor ICs

  16. Binary Arithmetic - Addition • Two binary numbers are performed in exactly the same manner as the addition of decimal numbers. • Addition Example: X 229 1 1 1 0 0 1 0 1 Y + 46 + 0 0 1 0 1 1 1 0 275 1 0 0 0 1 0 0 1 1

  17. Binary Subtraction • Two binary numbers are subtracted by subtracting each pair of bits together with borrowing, where needed. • Subtraction Example: X 229 1 1 1 0 0 1 0 1 Y - 46 - 0 0 1 0 1 1 1 0 183 1 0 1 1 0 1 1 1

  18. Complements • Allow the representation of negative numbers. • Complements are used in digital computers for simplifying the subtraction operation. • Two types of complement for binary numbers: • One’s complement • Two’s complement • The 1’s complement of a binary number is formed by changing 1’s to 0’s and 0’s to 1’s Example: • The 1’s complement of 1011000 is 0100111 • The 1’s complement of 0101101 is 1010010

  19. Complements • The 2’s complement of a binary number is formed by adding 1 to the 1’s complement. 2’s complement = (1’s complement) + 1

  20. Complements • Alternative method to find 2’s complement: • Start at the right with the LSB and write the bits as they are up to including the first 1. • Do 1’s complements of the remaining bits. Example: • The 2’s complement of 1101100 is 0010100 • The 2’s complement of 0110111 is 1001001

  21. Negative Binary Number Representations • Signed-Magnitude Representation: • For an n-bit binary number: Use the first bit (most significant bit, MSB) position to represent the sign where 0 is positive and 1 is negative. Ex. 1 1 1 1 1 12 = - 12710 • Remaining n-1 bits represent the magnitude which may range from: -2(n-1) + 1 to 2(n-1) – 1 • This scheme has two representations for 0; i.e., both positive and negative 0: for 8 bits: 00000000, 10000000 • Arithmetic under this scheme uses the sign bit to indicate the nature of the operation and the sign of the result, but the sign bit is not used as part of the arithmetic. Sign Magnitude

  22. Combinational Arithmetic Circuits • Addition: • Half Adder (HA) • Full Adder (FA) • Carry Ripple Adders • Subtraction: • Half Subtractor • Full Subtractor • Borrow Ripple Subtractors • Subtraction using adders

  23. X 0 0 1 1 Y 0 1 0 1 S 0 1 1 0 C-out 0 0 0 1 Half Adder Truth Table: Inputs Outputs X Half Adder S C-OUT Y Block diagram Half Adder (HA) • Adding two single-bit binary values, X, Y produces a sum S bit and a carry out C-out bit. • This operation is called half addition and the circuit to realize it is called a half adder. • S(X,Y) = S m(1,2) • S = X’Y + XY’ • S = X Å Y • C-out(x, y, C-in) = S (3) • C-out = XY

  24. X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 C-in 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 C-out 0 0 0 1 0 1 1 1 Sum S X X XY XY Inputs Outputs 00 01 11 10 00 01 11 10 C-in C-in 1 1 6 6 0 0 2 2 4 4 0 1 0 1 1 1 3 3 5 5 7 7 1 1 C-in C-in Carry C-out Y Y 1 1 1 1 • S(X,Y, C-in) = Sm(1,2,4,7) • C-out(x, y, C-in) = Sm (3,5,6,7) Full Adder • Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit. Full Adder Truth Table S = X’Y’(C-in) + X’Y(C-in)’ + XY’(C-in)’ + XY(C-in) S = X Å Y Å(C-in) C-out = XY + X(C-in) + Y(C-in)

  25. Full Adder

  26. X’ X’Y’C-in Y’ C-in X’ Sum S X’YC-in’ Y C-in’ X Y C-in’ XY’C-in’ X Y XYC-in C-in’ Circuit X XY Y X XC-in C-out C-in Y YC-in C-in Full Adder • Full Adder Circuit Using AND-OR: X Y Full Adder C-out C-in S Block diagram

  27. X Y Full Adder C-out C-in S Full Adder • Full Adder Circuit Using X-OR:

  28. X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 C-in 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 C-out 0 0 0 1 0 1 1 1 Inputs Outputs • S(X,Y, C-in) = Sm(1,2,4,7) • C-out(x, y, C-in) = Sm (3,5,6,7) Full Adder • Full Adder Using two half adder • Use different theorem to get a simplified in X-OR form

  29. Full Adder • Full Adder Using two half adder C-out

  30. Full Adder • Full Adder Using two half adder X X Half Adder Half Adder S C-OUT Y C-in

  31. n-bit Carry Ripple Adders • An n-bit adder used to add two n-bit binary numbers can built by connecting in series n full adders. • Each full adder represents a bit position j (from 0 to n-1). • Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at the higher position j+1. • The output of a full adder at position j is given by: Sj = XjÅYjÅCj Cj+1 = Xj . Yj + Xj. Cj + Y . Cj • In the expression of the sum Cj must be generated by the full adder at the lower position j-1. • The propagation delay in each full adder to produce the carry is equal to two gate delays = 2 D • Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately: Total Propagation delay = 2 nD

  32. Inputs to be added X3X2X1X0 Y3Y2Y1Y0 4-bit Adder C4 C0 =0 C-in C-out X0 Y0 X2 X1 X3 Y2 Y1 Y3 S3 S2 S1 S0 Full Adder Full Adder Full Adder Full Adder C3 C2 C1 Data inputs to be added C4 C0 =0 C-in C-in C-in C-in C-out C-out C-out C-out Sum Output S0 S3 S1 S2 Sum output 4-bit Carry Ripple Adder Adds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 producing the sum S = S3 S2 S1 S0 , C-out = C4 from the most significant position j=3 Total Propagation delay = 2 nD = 8D or 8 gate delays

  33. Data inputs to be added X (X0 to X15) , Y (Y0-Y15) 4-bit Adder 4-bit Adder 4-bit Adder 4-bit Adder C12 C8 C4 C16 C0 =0 C-in C-in C-in C-in C-out C-out C-out C-out Sum output S (S0 to S15) Y3Y2Y1Y0 Y3Y2Y1Y0 Y3Y2Y1Y0 Y3Y2Y1Y0 X3X2X1X0 X3X2X1X0 X3X2X1X0 X3X2X1X0 S3 S2 S1 S0 S3 S2 S1 S0 S3 S2 S1 S0 S3 S2 S1 S0 Larger Adders • Example: 16-bit adder using 4, 4-bit adders • Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant position. Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder = 4 x 2 nD = 4 x8D = 32 D or 32 gate delays

  34. X 0 0 1 1 Y 0 1 0 1 D 0 1 1 0 B-out 0 1 0 0 Half Subtractor Truth Table: Outputs Inputs Difference D X Y X Half Subtractor D B-out B-OUT Y Half Subtractor • Subtracting a single-bit binary value Y from another binary value X (i.e. X -Y) produces a difference bit D and a borrow out bit B-out. • This operation is called half subtraction and the circuit to realize it is called a half subtractor. • D(X,Y) = Sm(1,2) • D = X’Y + XY’ • D = X Å Y • B-out(X, Y) = Sm(1) • B-out = X’Y

  35. X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 B-in 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 B-out 0 1 1 1 0 0 0 1 Difference D X X XY XY 00 01 11 10 00 01 11 10 B-in B-in 1 1 6 6 0 0 2 2 4 4 0 1 0 1 1 1 3 3 5 5 7 7 1 1 B-in B-in Y Y Full Subtractor • Subtracting two single-bit binary values, Y, B-in from a single-bit value X produces a difference bit D and a borrow out B-out bit. This is called full subtraction. Full Subtractor Truth Table: Inputs Outputs D = X’Y’(B-in) + X’Y(B-in)’ + XY’(B-in)’ + XY(B-in) D = X Å Y Å(B-in) Borrow B-out 1 1 1 1 • S(X,Y, B-in) = Sm(1,2,4,7) • B-out(x, y, B-in) = Sm(1,2,3,7) B-out = X’Y + X’(B-in) + Y(B-in)

  36. X’ X’Y’B-in Y’ B-in X’ Difference D X’YB-in’ Y B-in’ X Y B-in’ XY’B-in’ X Y XYB-in B-in’ X Y X’ X’Y Y Full Subtractor B-out B-in X’ X’B-in B-out B-in Y D YB-in B-in Full Subtractor • Full subtractor circuit using AND-OR

  37. X Y B-in X Y X’ X’Y Y Full Subtractor B-out B-in X’ X’B-in B-out B-in Y D YB-in B-in Full Subtractor • Full Subtractor Circuit Using X-OR: Difference D

  38. n-bit Borrow Ripple Subtractor An n-bit subtractor used to subtract an n-bit number Y from another n-bit number X (i.e X-Y) can be built in one of two ways: • By using n full subtractors and connecting them in series, creating a borrow ripple subtractor: • Each borrow out B-out from a full subtractor at position j is connected to the borrow in B-in of the full subtractor at the higher position j+1. • By using an n-bit adder and n inverters: • Find 2’s complement of Y by: • Inverting all the bits of Y using the n inverters. • Adding 1 by setting the carry in of the least significant position to 1 • The original subtraction (X - Y) now becomes an addition of X to two’s complement of Y using the n-bit adder.

  39. Inputs X3X2X1X0 Y3Y2Y1Y0 4-bit Subtractor B4 B0 =0 B-in B-out D3 D2 D1 D0 Difference Output D Data inputs to be subtracted X3 Y3 X2 Y2 X1 Y1 X0 Y0 B3 B2 B1 Full Subtractor Full Subtractor Full Subtractor Full Subtractor B4 B0 =0 B-in B-in B-in B-in B-out B-out B-out B-out D3 D2 D1 D0 Difference output D 4-bit Borrow Ripple Subtractor Subtracts two 4-bit numbers: Y = Y3 Y2 Y1 Y0 from X = X3 X2 X1 X0 producing the difference D = D3 D2 D1 D0 , B-out = B4 from the most significant position j=3

  40. 4-bit Subtractor Using 4-bit Adder Inputs to be subtracted Y3 Y2 Y1 Y0 X3 X2 X1 X0 4-bit Adder C4 C0 = 1 C-out C-in S3 S2 S1 S0 D3 D2 D1 D0 Difference Output

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