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Summary of Accomplishments

Summary of Accomplishments. Generated an Internal Boot ROM image Booted Leon in simulation Booted Leon in Hardware Control software SDRAM Implemented a Leon to FPX SDRAM controllor interface (Currently testing). Leon Boot Check. Message to user “LEON READY”. SRAM. data_in. data_out.

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Summary of Accomplishments

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  1. Summary of Accomplishments • Generated an Internal Boot ROM image • Booted Leon in simulation • Booted Leon in Hardware • Control software • SDRAM • Implemented a Leon to FPX SDRAM controllor interface (Currently testing)

  2. Leon Boot Check Message to user “LEON READY” SRAM data_in data_out Leon Boot Monitor ‘Z’ SRAM_OE CpuData Leon Processor CpuAddr

  3. Boot Rom Modifications Set Config registers Set Config registers Set up dedicated SRAM space Set up dedicated SRAM space Wait for Event ld count 200 Wait for Event Load: ld reg value Load: ld reg value dec count btst 1 reg be “CheckReady” be “Load” btst 1 reg be “Load” Wait for Start CheckReady: ld reg ProgAddr cmp 0 reg be “CheckReady” nop jmp reg Original Leon Boot code Modified Leon Boot code

  4. Leon Control Hardware Message to user “LEON READY” SRAM data_in data_out Leon Control State Machine Check for CpuAddr = CheckReady ‘0’ LeonGo CpuAddr LeonGo UserAddr ‘Z’ LeonGo UserStart SRAM_OE CpuData UserData Leon Processor CpuAddr

  5. Interaction with LEON • Basic steps to interface LEON/SRAM: • Wait for “LEON READY” message • Load Program to SRAM • Send LEON “START” message • Wait for “LEON READY” message • Read results from SRAM

  6. Goals For Next Week • Have Leon load a simple program from SRAM • Modify Boot Rom image • Intergrate LEON controller state machine • Interface to control software • Load Program (Write SRAM) • Start Program • Read Results ( Read SRAM)

  7. SDRAM Interface • Implemented Adapter connecting AMBA bus with SRAM Controller • Not fully tested • Does not yet Support Burst Transfers • Burst Transfers • FPX SDRAM Controller Supports Burst Transfers up to 256 words • Sequential Access only • Must know the burst length at start of transfer • AMBA protocol supports sequential and non-sequential bursts • Burst Length is variable

  8. SDRAM Interface • Goals • Insure that current adapter works in all cases • Add support for special cases of bursting • Support for sequential bursts of short lengths • No burst support for writes • Integrate into FPX wrappers

  9. Control S/W Architecture Internet web page Java UDP Client H/W Java Emulator of the H/W

  10. Control S/W web page

  11. Java Server receiving the packet

  12. Goals • Test H/W from build.arl.wustl.edu • Document Cross-compiler procedure • Look into debugger, time permitting

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