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Eric Björklund LANSCE-8 Controls Software (LA-UR-05-2848)

LANSCE Master Pattern Generator. LANSCE Master Pattern Generator. Eric Björklund LANSCE-8 Controls Software (LA-UR-05-2848). Features of the LANSCE Timing System. 96 Timing Gates. Centrally Generated. Distributed on Coax and Fiber From MPG. 120 Hz Operation.

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Eric Björklund LANSCE-8 Controls Software (LA-UR-05-2848)

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  1. LANSCE Master Pattern Generator LANSCE Master Pattern Generator Eric Björklund LANSCE-8 Controls Software (LA-UR-05-2848)

  2. Features of the LANSCE Timing System • 96 Timing Gates. • Centrally Generated. • Distributed on Coax and Fiber From MPG. • 120 Hz Operation. • Machine cycle is 8.222 milliseconds. • Start of cycle synchronized with AC Line crossing(positive and negative slope). • Timing Gates Clocked by 2.8 Mhz Ring Revolution Frequency. • 1 Second Super-Cycle (120 Cycles). • Versatile (and therefore complex) facility: • 3 flavors of H- beam • 2 flavors of H+ beam • Single Shot & Continuous Mode Capability for Any Beam Flavor.

  3. Special Requirements (Mostly Age-Related) • Reliability is important. • It can take up to 2 hours to recover from a 1 second loss of RF-gates. • Evenness is also important. • Absolute requirement for some gates: • RF gates • Neutron Choppers • Less of an issue for other gates: • Isotope production • Single-Shot experiments • Irradiation Experiments

  4. Current Architecture of LANSCE Timing System Timing Gates • Star configuration • 4 redundant gate generator sets in 2 CAMAC crates. • Gate generators are loaded by Master Timer computer, then run independently. • Master Timer computer checks the output of the gate generators and automatically switches to another set when a discrepancy is seen. Timing Distribution Master Timer Timing Gate Generators MUX

  5. Tools To Generate the Pattern – Delay and Width ; ; Low Frequency RF Gate ; M(LFRF) = 30 D(LFRF) = D(LBEG) - 400 E(LFRF) = D(SREX) ; ; Storage Ring Extraction Window ; M(SREW) = 30 D(SREW) = E(LBEG) - 50 E(SREW) = D(EKLF) ; ; Storage Ring Extraction Gate ; M(SREX) = 30 D(SREX) > D(SREW) + 50 L(SREX) = 10 ; ; LANSCE Chopper Synchronization Gate ; RR(LSYC) = 20 D(LSYC) = D(T0) - 100 E(LSYC) = D(EKLF) + 125 ; ; LANSCE Fast Chopper Synch Gate ; RR(LFCG) = 120 M(LFCG) = 0 D(LFCG) = D(EKLF) L(LFCG) = 25 • LANSCE uses a rule-based system to generate the placement of timing gates within a machine cycle. • Configuration file contains rules for either automatically setting a gate’s delay and width, or providing limits on acceptable values. • A special parser reads the configuration file and generates a subroutine that is compiled and linked into the MPG program.

  6. Tools To Generate the Pattern – Super-Cycle Layout • “Mode” rules determine which gates may occur on which machine cycles. • Cycles are assigned based on requested rep-rate and mode constraints. • Keep the three H- flavored gates on separate cycles. • Keep the two H+ flavored gates on separate cycles. • Keep the high-power H+ flavored gates and high-power H- flavored gates on separate cycles. • Prioritizes order in which gates are assigned. Mode Name Base Gate Definition 0 ANY None May occur on any cycle 1 201 PREDECESSOR 201R May only occur on cycles preceding 201R gates 2 805 PREDECESSOR 805R May only occur on cycles preceding 805R gates 3 RFAL PREDECESSOR RFAL May only occur on cycles preceding RFAL gates 4 RFAM PREDECESSOR RFAM May only occur on cycles preceding RFAM gates 5 RFAS PREDECESSOR RFAS May only occur on cycles preceding RFAS gates 6 201 COINCIDENT 201R May only occur on cycles with 201R gates 7 805 COINCIDENT 805R May only occur on cycles with 805R gates

  7. Tools To Generate the Pattern – Super-Cycle Layout • Theoretical Framework Developed for Evenly Distributing Gates Across the Super-Cycle. • Completely even distribution for unconstrained gates with rep-rates that evenly divide 120.O(n) time. • Most even distribution possible for unconstrained gates with rep-rates that do not evenly divide 120.O(n) time. • Most even distribution possible for constrained gates whose “ideal” patterns map into the available cycles.O(n2) time. • Good heuristics for constrained gates whose “ideal” patterns do not map into the available cycles.O(n) – O(n5) time.

  8. Tools To View The Generated Pattern • “Micro” view of a single “generic” cycle. • Shows gate relationships within the machine cycle. Time Plot

  9. Tools To View The Generated Pattern • “Macro” view of the Super-Cycle. • Shows which gates are assigned to which cycles. Rep-Rate Plot

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