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Simulating Front-end Electronics and Integration with End-to-end Simulation

This workshop explores the simulation of front-end electronics and integration using end-to-end simulation techniques. Topics include time stretchers, TDCs, and the IBM SiGe BiCMOS 8HP process.

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Simulating Front-end Electronics and Integration with End-to-end Simulation

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  1. Simulating Front-end Electronics and Integration with End-to-end Simulation Fukun Tang Enrico Fermi Institute University of Chicago With Karen Byrum and Gary Drake (ANL) Henry Frisch, Mary Heintz and Harold Sanders (UC) Pico-Sec Simulation Workshop University of Chicago 12/12/06

  2. Harold’s TOF System dum Pico-Sec Simulation Workshop University of Chicago 12/12/06

  3. Time Stretcher TDC MCP_PMT Output Signal Start 500pS Reference Clock Stop Tw “fine” time interval psFront-end

  4. IBM SiGe BiCMOS 8HP Process • 130-nm Technology • SiGe Hetero-junction Bipolar Transistors • fT (high performance): 200GHz, BVceo=1.7V, BVcbo=5.9V • fT (high breakdown): 57GHz, BVceo=3.55V, BVcbo=12V • High-Q Inductors and Metal-Isolator-Metal Capacitors • 4 Types of Low-tolerance Resistors with Low and High Sheet Resistivity • n+ Diffusion, Tantalum Nitride, p+ Polisilicon and p- Polisilicon • Electrically Writable e-Fuse • CMOS Transistors (VDD=1.2V or 2.5/3.3V) • Twin-well CMOS • Hyperabrupt Junction and MOS Varactors • Deep Trench and Shallow Trench Isolations • 3 to 5 Copper Layers and 2 Aluminum Layers (up to 3 thick layers) • Wire-bond or Controlled Collapse Chip Connect (C4) Solder-bump Terminals

  5. Cadence Custom IC Design Flow for IBM 8HP Design Specification Library, tech files Virtuoso Schematic Schematic Capture Models Analog Design Environment (ADE) AMS Design Environment (AMS) Circuit Simulations Tech File, DRC, PCell Virtuoso XL Layout Chip Assembly Router Cell/Chip Layout Verification and RF Parasitic Extraction IBM 8HP PDK Tech File , DRC Assura DRC/LVC, RCX Post-Layout Simulations Models, RCX ADE, AMS Simulations Tech File Mask Generation GDSII Stream Out Tech, Foundry Rules Validation DRC, Filler Generation Tape-Out

  6. Interface to Other Simulation Tools ASCII files: Waveform time-value pair ASCII files: Waveform time-value pair Tube Output Signals from Simulation Cadence Virtuoso Analog Environment Or Cadence Virtuoso AMS Environment System Simulation Results Tube Output Signals from Scope Spectre Netlist Spectre Library Spectre Netlist (Cadence Spice) Custom Chip Schematic IBM 8HP PDK Cadence Simulator

  7. Waveform Time-value Pair Format

  8. 02/2007 MOSIS Submission (2GHz VCO) 2GHz VCO Schematics Simplified VCO Core Schematic • SiGe HJT, negative resistance differential VCO • On-chip high-Q LC tank • High Frequency PN diode Varactors • Capacitor voltage dividers • 50-ohm line drivers

  9. VCO Simulation Result Output Waveforms Phase Noise -97dBc/HzEquivalents to Cycle-to-cycle time-jitter of 5 fs V-F Transfer Function Tuning Range=7.5%

  10. Conclusion We entered a completely different world than most of us live in. We have lots to learn, lots need to be done. A journey of 1000 miles begins with a single step. ---Lao Tzu (Laozi), 600 B.C. Pico-Sec Simulation Workshop University of Chicago 12/12/06

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