Continuous Assignments

1. Continuous Assignments

2. Combinational Logic Circuits • each output of a Combinational Logic Circuit • A function of the inputs - Mapping functions (fo, f1, f2, …fm) • the outputs are updated immediately after the inputs change • Don’t forget the propagation delay in real circuits

3. Dataflow Modelling • only model behaviour of combinational logic circuits • assign a value to a net using continuous assignment (CA) statement • continuous assignment corresponds to combinational logic, without requiring explicit instantiation of gates • flip-flops and latches can NOT be created using continuous assignment • continuous assignments are always active • source order of the CA statements does not impact the design • CA statements are executed concurrently

4. Continuous Assignments meaning • A continuous assignment is the most basic statement in dataflow modeling, used to drive a value onto a net. • A continuous assignment replaces gates in the description of the circuit and describes the circuit at a higher level of abstraction. • A continuous assignment statement starts with the keyword assign.

5. A simple dataflow example Assign c = a&&b; • “assign” is the keyword carrying out the assignment operation. This types of assignment is called a continuous assignment. • a and b are operands – typically single-bit logic variables. • “&&” is a logic operator. It does the bit-wise AND operation on the two operands a and b. • “=“ is an assignment activity carried out. • C is a net representing the signal which is the result of the assignment.

6. Continuous Assignments syntax • //Syntax of assign statement in the simplest form <continuous assign> ::= assign <drive strength> ? <delay>?<list of assignments>; • Example: • / / Continuous assign. out is a net. i1 and i2 are nets. assign out = i1 & i2; • // Continuous assign for vector nets. addr is a 16-bit vector net // addrl and addr2 are 16-bit vector registers. assign addr[l5:0] = addrl_bits[l5:0] * addr2_bits[l5:0]; • // Concatenation. Left-hand side is a concatenation of a scalar // net and a vector net. assign {c_out, sum[3:0]) = a[3:0] + b[3:0] + c_in;

7. Dataflow example AND-OR-INVERT

8. Example: Multiplexer

9. Compare the two Verilog modules and comment their final implementations. Example Ans: The ‘+’ operator is not bound directly to physical gates • Example: Half Adder

10. Example: Full Adder

11. Example: Given: Tpd(AND) = 10ns Tpd(XOR) = 15ns `timescale 1ns/100ps module Half_Adder (CO, SUM, A, B); output CO, SUM; input A, B; assign#10 CO = A & B; assign#15 SUM = A ^ B; endmodule

12. Example : 4X1 MuX using logic equations // Module 4-to-1 multiplexer using data flow logic equation // Compare to gate-level model module mux4_to_1 (out, i0, i1, i2, i3, s1, s0); // Port declarations from the I/O diagram output out; input i0, i1, i2, i3; input s1, s0; // Logic equation for out assign out = (~s1 & ~s0 & i0) | (~s1 & s0 & i1) | (s1 & ~s0 & i2) |(s1 & s0 & i3) ;

13. 4-to-1 Multiplexer, Using Conditional Operators / / Module 4-to-1 multiplexer using data flow. Conditional operator. / / Compare to gate-level model module multiplexer4-to-1 (out, i0, i1, i2, i3, s1, s0); / / Port declarations from the I/O diagram output out; input i0, i1, i2, i3; input s1, s0; / / Use nested conditional operator assign out = s1? ( s0 ? i3 : i2) : (s0 ? il : i0) ; endmodule