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A 40 mV /4 uW CMOS Colpitts Oscillator with Additional Positive Feedback at 2.12 GHz

A 40 mV /4 uW CMOS Colpitts Oscillator with Additional Positive Feedback at 2.12 GHz. Rodrigo Eduardo Rottava Fernando Rangel de Sousa. Outline. Introduction Proposed Topology Analysis Design Post-layout Simulations Conclusions. Introduction.

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A 40 mV /4 uW CMOS Colpitts Oscillator with Additional Positive Feedback at 2.12 GHz

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  1. A 40 mV/4 uW CMOS ColpittsOscillatorwithAdditional Positive Feedback at 2.12 GHz Rodrigo Eduardo Rottava Fernando Rangel de Sousa

  2. Outline • Introduction • ProposedTopology • Analysis • Design • Post-layoutSimulations • Conclusions

  3. Introduction Theaim: newtopology to reducepowerconsumptionandsupplyvoltageofradio-frequencyoscillators.

  4. Introduction Theaim: newtopology to reducepowerconsumptionandsupplyvoltageofradio-frequencyoscillators. How: to add a new positive feedback technique in a classicalColpittsoscillator.

  5. Introduction Theaim: newtopology to reducepowerconsumptionandsupplyvoltageofradio-frequencyoscillators. How: to add a new positive feedback technique in a classicalColpittsoscillator. Applications: WBAN’s (ultra-lowpowerconsumption).

  6. Outline • Introduction • ProposedTopology • Analysis • Design • Post-layoutSimulations • Conclusions

  7. ColpittsOscillator OscillationCriteria: Highlevelrepresentation

  8. ColpittsOscillator OscillationCriteria: Highlevelrepresentation ColpittsOscillator

  9. ColpittsOscillator OscillationCriteria: Highlevelrepresentation ColpittsOscillator

  10. Adding Feedback Source admittanceLg:

  11. Adding Feedback Source admittanceLg:

  12. Adding Feedback Source admittanceLg: Byusingthosetwofeedback sources it is possible to reducethe bias current. Proposedtopology.

  13. Outline • Introduction • ProposedTopology • Analysis • Design • Post-layoutSimulations • Conclusions

  14. Small-SignalRepresentation Proposedtopology

  15. Small-SignalRepresentation CircuitLosses Proposedtopology Small-signalrepresentation

  16. Small-SignalRepresentation CircuitLosses Proposedtopology Small-signalrepresentation

  17. Small-SignalRepresentation CircuitLosses Proposedtopology Small-signalrepresentation

  18. Small-SignalRepresentation CircuitLosses Proposedtopology Small-signalrepresentation

  19. Small-SignalRepresentation CircuitLosses Proposedtopology Small-signalrepresentation

  20. Requiredgms Total source transconductance: Total draintransconductance: CircuitLosses 1stoscillationcriterion: Therequiredgmsin order to start-uptheoscillator:

  21. OscillationFrequency 2ndoscillationcriterion: Theoscillationfrequency is givenby: where:

  22. Reducingtherequiredgms Requiredgms:

  23. Reducingtherequiredgms Requiredgms: Twostrategies to reducetherequiredgmswerestudied.

  24. Reducingtherequiredgms Requiredgms: Twostrategies to reducetherequiredgmswerestudied. a) Optimum capacitor ratio:

  25. Reducingtherequiredgms Requiredgms: b) Gateinductivedegeneration:

  26. Reducingtherequiredgms Requiredgms: b) Gateinductivedegeneration: For |α|, |β| < 0

  27. Reducingtherequiredgms Requiredgms: b) Gateinductivedegeneration: For |α|, |β| < 0 Nevertheless, for

  28. EffectofLg EffectofLgonthe input conductanceofthe one-port network.

  29. EffectofLg EffectofLgonthe input conductanceofthe one-port network.

  30. Outline • Introduction • ProposedTopology • Analysis • Design • Post-layoutSimulations • Conclusions

  31. Design Flow DC Characterization

  32. Design Flow DC Characterization GateInductor

  33. Design Flow DC Characterization GateInductor OptimumCapacitiveRatio

  34. Design Flow DC Characterization GateInductor OptimumCapacitiveRatio Minimumgms?

  35. Design Flow DC Characterization GateInductor OptimumCapacitiveRatio Minimumgms? No Decrease VDD

  36. Design Flow DC Characterization GateInductor OptimumCapacitiveRatio Minimumgms? No GateInductor Yes OptimizedLow-VoltageOscillator

  37. Specifications • Oscillatorat 2.4 GHz in CMOS 130 nmusing a zero VTH transistor. • Buffer in order to adapte theoscillatorwiththespectrumanalyzer.

  38. Specifications • Oscillatorat 2.4 GHz in CMOS 130 nmusing a zero VTH transistor. • Buffer in order to adapte theoscillatorwiththespectrumanalyzer. Oscillator Core

  39. Specifications • Oscillatorat 2.4 GHz in CMOS 130 nmusing a zero VTH transistor. • Buffer in order to adapte theoscillatorwiththespectrumanalyzer. Buffer

  40. Specifications • Oscillatorat 2.4 GHz in CMOS 130 nmusing a zero VTH transistor. • Buffer in order to adapte theoscillatorwiththespectrumanalyzer. SpectrumAnalyzer

  41. Parameters

  42. Parameters

  43. Parameters

  44. Final Layout Technology: IBM 130 nm. M1 = Zero-VTH transistor Area: 0.9 mm² Lg L1 LRFC

  45. Final Layout Technology: IBM 130 nm. M1 = Zero-VTH transistor Area: 0.9 mm² M1 IB M2

  46. Final Layout Technology: IBM 130 nm. M1 = Zero-VTH transistor Area: 0.9 mm² VDD GND RF OUT B1 B2

  47. Outline • Introduction • ProposedTopology • Analysis • Design • Post-layoutSimulations • Conclusions

  48. Post-layoutSimulation ID Vout TransientSimulation (loadedoscillator) Output voltageanddraincurrent

  49. Post-layoutSimulation 30 mV ID Vout TransientSimulation (loadedoscillator) Output voltageanddraincurrent

  50. Post-layoutSimulation VDD ID = 4 µW ID Vout TransientSimulation (loadedoscillator) Output voltageanddraincurrent

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