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RF Microelectronic

RF Microelectronic. LNA and Mixer Oscillator. Contents. Introduction Basic concepts Digital modulation, Spectral control, Detection Multiple access standards, TDM, CDM, OFDM TRx architecture LNA and Mixer Oscillator Frequency Synthesizer Power Amplifier. Section 6. LNA and Mixers

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RF Microelectronic

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  1. RF Microelectronic LNA and Mixer Oscillator

  2. Contents • Introduction • Basic concepts • Digital modulation, Spectral control, Detection • Multiple access standards, TDM, CDM, OFDM • TRx architecture • LNA and Mixer • Oscillator • Frequency Synthesizer • Power Amplifier

  3. Section 6 • LNA and Mixers • LNA • Input matching vs. NF • BJT vs. CMOS • BW enhancement • Mixer • BJT Mixers • CMOS Mixers • Noise in Mixers • Cascaded stages

  4. LNA Figures of Merit • Frequency • Noise Figure • Linearity (P-1dB, IIP3) • Bandwidth and Q • Gain S21 • Power Consumption • Supply Voltage • S-Parameters • Gain S21 • Input Matching S11 • Output Matching S22 • Reverse Isolation S12 • Stability • Image Rejection Capability

  5. Typical Figures of Merit

  6. LNA Design • Input Matching Network • Noise and Linearity Consideration • Output Loading and Gain • Output Matching Network • Stability • Differential Design

  7. Noise Figure of LNA • LNA, the first gain stage in the receive path its Noise figure directly adds to that of the system Duplexer Noise Figure ~ 2dB System Noise Figure=4dB LNA noise Figure =2dB 8dB

  8. Noise Figure of LNA • LNA=2dB using BJT: =2KTgm (shot noise) 4KTrb

  9. Noise Figure of LNA • For NF=2dB Req < 29Ω Q1 must be relatively large and biased at a high current • Finger structure reduces rb but increases capacitance Bandwidth reduction

  10. Minimum Gain of LNA • Defined by Three parameters: • Loss of the image-reject filter • Noise Figure of mixer • IP3 of the Mixer • For example: • Filter loss=4~5 dB • Mixer noise figure=10dB min. Gain=20dB • Mixer IP3=+5dBm • Input-referred noise is suppressed • reasonable equivalent IP3 is maintained

  11. Input and Output Matching • Input Impedance is 50Ω because it comes out of the antenna • Output Impedance can be>=50Ω whether it goes to IC • The quality of the input matching is expressed by: Input Return Loss=20log|Γ| Γ=the reflection coefficient with respect to a source impedance R0 For Impedance Matching: Γ<0.2

  12. Measuring S11 and S21

  13. Measuring S11 and S21

  14. Input and Output Matching • Γ=0.2 Zin=35Ω_65Ω • |S11|35=((35-50)/(35+50))^2|dB=-15dB • |S11|65=((65-50)/(65+50))^2|dB=-17.6dB • In RF Circuits : • Impedance matching Max Power Transfer • In LNA Design: • R sopt We accept mismatch in the first stage But we try to select the device in a way to have Rsopt~50Ω Matching circuit 50Ω Rsopt 50Ω 50Ω 50Ω 50Ω 50Ω 50Ω

  15. Input and Output Matching • In IC design when the receiver sensitivity is very important e.g. GPS, external discrete LNA placed on the PCB is desirable • In mass productive ICs e.g. for Mobile handsets, we try to design input LNA, • LNA output Impedance must also equal 50Ω to have the minimum loss and ripple in driving Image-Reject Filter Zin=Rsopt~50Ω

  16. LNA stability • Due to feedback from the output to input, the circuit may become unstable for certain amounts of source and load Impedance • The amount of feed-back can also set the reverse isolation of the amplifier which is important for LO radiation.

  17. LNA stability • Stern Stability Factor : • If K>1 & Δ<1 The circuit is unconditionally stable • Difficulty: S parameters must be calculated for a wide frequency range to ensure that K>1 at all frequencies

  18. LNA stability • If S12 0 then: K ∞ Δ S11.S22<1 (both S11 & S22 inside the unit circle of the smith chart) • This function is called “Neutralization” of the return path

  19. Stabilization by Neutralization • L1 and C1 actually tune out the parasitic capacitance At a frequency thus S12=0

  20. Stabilization by Cascoding • In IC design the feedback can be suppressed by cascode configuration Variation of the node X is small due to Vb so the effect on Vin is low enough to reduce S12 X

  21. Is the LNA stable anyway? • Vcc and GND leakage paths and substrate of ICs still have to be considered • Isolating Vcc and GND is a solution • Differential structure is useful for c.m. signal rejection • Problem: • Differential LNA design is not easy because of matching constraints

  22. Is the LNA stable anyway?

  23. PCB Ground Consideration

  24. Impedance matching in MOS LNA • A common-source stage in order to create 50Ω input Impedance

  25. Impedance matching in MOS LNA Proper selection of 2CL/gmCF makes 50Ω input resistance but the drawback is the relatively low voltage gain at high frequenciesdue To bandwidth limitation at the output node

  26. Resistive Termination • In high frequencies, Capacitive part of the input impedance must be cancelled by an external inductor • Noise figure is at least 3dB (NF=1+Rs/RP , Rs = RP)

  27. Input Resistive Termination by Negative Shunt Feedback • Low input impedance with a 50Ω real part can be obtained

  28. Input Resistive Termination by Negative Shunt Feedback • Drawbacks: • Active feedback injects noise in the input of the circuit • Frequency stability can be ruined because of the creation of a loop • Either compensation (BW reduction) or oscillation risks should be accepted

  29. Common-gate stage design • Trade-off between noise figure and input matching

  30. Common-gate stage design • Input resistance of 50Ω is achieved by proper Bias parameters • The drawback is worse Noise Figure:

  31. Common-gate stage design • Long channel devices (1-10μm) γ=0.66 • Short channel devices(0.18-0.5μm) γ=3~4 • High noise Figure in recent technology

  32. Resistive termination by Inductive Degeneration LS X Vref For Bias

  33. Resistive termination by Inductive Degeneration • Freedom in tuning Zin is obtained • L1 is tuned to have 50Ω by the first statement • LS is added to reject the second and third statement • Vref is placed for Bias • The circuit is designed in an iterative process • L1 degenerates the gain

  34. Bipolar LNA with Replica Biasing • I1 is passed through Q1 so thermal matching is obtained

  35. Bipolar LNA • R1 & R2: • Compensate the effect of β (Base Current) • Reducing the value of C1 that rejects the Biasing circuit’s Noise (Since the input Impedance is increased, smaller capacitor can be used) • R2 causes approximately equal VBE for transistors so thermal matching is obtained • Noise of R1 can not be rejected because the signal will be grounded if the capacitor is placed before R1

  36. Bipolar LNA • Noise Figure is considered as the following: Shot noise of Collector 4KT/2gm Shot noise of Base 4KTgm/2β

  37. IP3 calculation Power voltage

  38. Comparison • With MOS, better values of iip3 is considerable • MOS does not have shot noise so we do not have an optimum value for noise • In order to have controlled NF, discrete circuit has to be implemented because inside the IC, β and Rb are not controllable

  39. Some State-Of-The-Art LNAs • MEYER & MACK • IEEE Journal of Solid-State Circuits, Vol.29, PP.350-355, March 1994 • Common-Base LNA • CMOS LNA: Karanicolas • IEEE Journal of Solid-State Circuits, Vol.31, PP.1939-1944, December 1996 • LNA implemented with MESFETs

  40. A 900MHz Bipolar LNA • MEYER & MACK Defines DC level of the output Opens the feedback at high frequencies Negative feedback

  41. A 900MHz Bipolar LNA • First Stage: • provides much of the gain • controls Noise Figure • Second Stage: • Lower Gain • Controls Zout • Rf & RE effectively linearize the second stage • Le improves ip3 because of its re like effect • re is proportional to VT, ip3 (voltage)=2√2VT

  42. A 900MHz Bipolar LNA • Thermal stability of the gain is considered as follows:

  43. A 900MHz Bipolar LNA • Le also provides conjugate matching of the input • With proper choice of gm, Le, CΠ: • The last two terms cancel

  44. Common-Base LNA • The source resistance Rs linearizes the input-output characteristic Rin

  45. Common-Base LNA • Rin is used to reduce current but it worsens the NF • Although BJT, but the circuit is very linear • 1/gm<<Rs so in the voltage divider, the lower voltage causes little variation and consequently better linearity

  46. Common-Base LNA • With Rin=0 Rs=1/gm=50Ω iip3≈-6.8dBm • High reverse isolation is achieved if the base bias is properly bypassed • Relatively high noise figure is the drawback

  47. MOS LNA • Karanicolas M3 For Bias

  48. MOS LNA • Vref and W/L of M3 changes the Bias current • The capacitor makes the gain for M1 otherwise bypasses the feedback in AC • The bias current is reused to provide a higher equivalent transconductance: (gm1+gm2) • The circuit is followed by a similar stage so as to drive a 50-Ω load

  49. MOS LNA • 900-MHz LNA & 2.7-V Vcc in CMOS 0.5μm technology • NFmin=1.9 dB • External matching network • Gain=15.6 dB • iip3=-3.2 dBm • 20mW power consumption 7mA

  50. LNA implemented with MESFETs • Recently implemented with CMOS

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