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Scalable Don’t-Care-Based Logic Optimization and Resynthesis

Scalable Don’t-Care-Based Logic Optimization and Resynthesis. Alan Mishchenko, University of California, Berkeley Robert Brayton, University of California, Berkeley Jie-Hong Roland Jiang , National Taiwan University Stephen Jang , Xilinx, Inc. Outline. Motivation

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Scalable Don’t-Care-Based Logic Optimization and Resynthesis

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  1. Scalable Don’t-Care-Based Logic Optimization and Resynthesis Alan Mishchenko, University of California, Berkeley Robert Brayton, University of California, Berkeley Jie-Hong Roland Jiang, National Taiwan University Stephen Jang, Xilinx, Inc

  2. Outline • Motivation • Brief history of don’t-cares • Algorithm overview • Algorithm components • Experimental results • Conclusion

  3. Network after mapping Optimized network Motivation resynthesis f f  Applications • tech-independent synthesis • post-mapping delay/area optimization • placement-aware resynthesis Requirements • substantial logic restructuring • flexibility to solve many optimization tasks • reasonable runtime for large designs Our solution • SAT-based re-synthesis • with don’t-cares • using resubstitution

  4. Brief History of Don’t-Cares • Previous century work (1960-2000) • Permissible functions (Saburo Muroga, 1989) • Compatible observability don’t-care (Hamid Savoj, 1992) • Complete rather than compatible don’t-cares (2002) • SAT-based don’t-care computation (2005) • Interpolation-based optimization with don’t-cares without explicitly computing don’t-cares (this talk)

  5. Background Summary • Assuming familiarity with • Networks and nodes • Cuts and cones • Don’t-cares and resubstitution • SAT-based interpolation

  6. Resubstitution with Don’t-Cares Consider all or some nodes in Boolean network For each node • Create window • Select possible fanin nodes (divisors) • For each candidate subset of divisors • Rule out some subsets using simulation • Check resubstitution feasibility using SAT • Compute resubstitution function using interpolation • A low-cost by-product of completed SAT proofs • Update the network, if there is an improvement

  7. Resubstitution Resubstitution considers a node in a Boolean network and expresses it using a different set of fanin nodes X X Computation can be enhanced by don’t cares

  8. Window POs m = 3 n = 3 Window PIs Windowing a Node in the Networkfor Don’t-Care Computation • Definition • A window for a node in the network is the context in which the don’t-cares are computed • A window includes • n levels of the TFI • m levels of the TFO • all re-convergent paths captured in this scope • Window with its PIs and POs can be considered as a separate network Boolean network (k-LUT mapped circuit)

  9. Don’t-Care Representation Miter for don’t-care computation If output is 1, input is a care If output is 0, input is a don’t-care … Same window with inverter Window f f

  10. g1 g1 g3 g3 g2 g2 C(x) F(x) F’(x) h(g) C(x) F(x) Resubstitution with Don’t Cares • Given: • node function F(x) to be replaced • care set C(x) for the node • candidate set of divisors {gi(x)} for expressing F(x) • Find: • A resubstitution function h(y) such that F(x) = h(g(x)) on the care set • SPFD Theorem: • Function h exists if and only if each pair of care minterms, x1 and x2, distinguished by F(x), is also distinguished by gi(x) for some i

  11. Checking Resubstitution using SAT Miter for resubstitution check h(g) SPFD Theorem in practice Comments: • Note use of care set, C. • Resubstitution function exists if and only if the SAT problem is unsatisfiable • Function h(g) is computed using interpolation

  12. Experimental Setup • Implemented in ABC (command “mfs”) • The SAT solver is a modified version of MiniSat-1.14C, by Niklas Een and Niklas Sorensson • The algorithm was applied to a mapped network and attempted resubstitution for each LUT to reduce (a) area, (b) number of fanins. • Experiments targeting networks after FPGA mapping into 6-LUTs on an Intel Xeon 2-CPU with 8Gb of RAM • The resulting networks have been verified using equivalence checker in ABC (command “cec”) • Optimization scripts used • Baseline: result of (dc2 –l; dc2 –l; if –C 12)1 • Choices: best result of (st; dch; if –C 12)4 • Mfs: best result of (st; dch; if –C 12; mfs –W 4)4

  13. Results for Academic Benchmarks

  14. Results for Industrial Benchmarks

  15. Conclusion • Introduced a new SAT-based logic optimization engine • uses rugged windowing scheme without previous limitations • uses SAT solver for all aspects of functional manipulation • designed for scalability and applicable to large industrial circuits • Showed promising experimental results • academic benchmarks (10-40% in area, 10% in delay) • industrial benchmarks (7% in area, 8% in delay) • improvements can be made even on top of strong synthesis • Future work • improving runtime by fine-tuning simulation and SAT • experimenting with timing-driven and power-aware resynthesis • extending don’t-care computation to work with white-boxes • global circuit restructuring using interpolation

  16. The End

  17. Algorithm Overview nodeSatBasedResynthesis( node, parameters ) { window = nodeWindow( node, parameters ); divisors = nodeDivisors( node, window, parameters ); cands = nodeResubCandsFilter( node, window, parameters ); best_cand = NULL; for each candidate set c in cands { if ( best_cand != NULL && resubCost(best_cand) < resubCost(c) ) continue; if ( !resubFeasible( node, window, c ) ) continue; best_cand = c; } if ( best_cand != NULL ) { best_func = nodeInterpolate( sat_solver, node ); nodeUpdate( node, best_cand, best_func ); } }

  18. Divisor Selection • Divisor is a candidate fanin of the pivot node after resubstitution • Divisor computation: • Partition window PIs into (a) those in the TFI node of the pivot (b) the remaining window PIs • Add nodes between the pivot and window PIs of type (a), excluding the node and the node’s MFFC • Add nodes in the window if their structural support has no window PIs of type (b) • Do not collect divisors whose level exceed a limit • Do not collect more than a given number of divisors Window POs m = 3 Pivot node k = 3 type (b) type (b) type (a) Window PIs

  19. Resubstitution • Resubstitution of F(x) with care set C(x) and candidate functions {gi(x)} exists iff every pair of care minterms, x1 and x2, distinguished by F(x), is also distinguished by gi(x) for some i • That is, if information of F(x) does not exceed that of {gi(x)} Example: Given F = (ab)(bc), C = 1 Two candidate sets: {y1= a’b, y2 = ab’c}, {y3= a b, y4 = bc} Set {y1, y2} is feasible Set {y3, y4} is infeasible Counter-example: x1 = 100, x2 = 101

  20. Computing Dependency Function • Definition of the interpolant: • Consider A(x, y) and B(y, z), such that A(x, y) B(y, z) = 0, where x and z appear only in the clauses of A and of B, respectively, and y are variables common to A and B. • An interpolant of function A(x, y) w.r.t. function B(y, z) is a Boolean function, I(y), depending only on the common variables y, such that A(x, y) I(y) and I(y)  (y, z). • Problem: • Find function h(g), such that h(g(x)) can replace f(x) on care set C(x), that is, C(x)  [h(g(x))f(x)]. The dependency functionh(g) expresses the node, f(x), in terms of {gi}. • Solution: • Prove the corresponding SAT problem “unsatisfiable” • Derive unsatisfiability proof [Goldberg/Novikov, DATE’03] • Derive interpolant from the unsatisfiability proof using McMillan’s procedure [CAV’03] (assume A and B as shown on previous slide) • Use interpolant as the dependency function, h(g)

  21. Resynthesis Heuristics • Resynthesis is attempted for each node • Window, divisors, and resubstitution candidates are computed • Heuristics for different minimization criteria: • Area • Try replacing each fanin whose reference counter is 1 • Fanin count • Try replacing each fanin • Delay • Try replacing each fanin that is on the critical path

  22. Previous Work • Optimization and mapping with internal flexibilities • S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney, “The transduction method-design of logic networks based on permissible functions”, IEEE Trans. Comp, Vol.38(10), pp. 1404-1424, Oct 1989 • H. Savoj. Don't cares in multi-level network optimization. Ph.D. Dissertation, UC Berkeley, May 1992. • V. N. Kravets and P. Kudva, “Implicit enumeration of structural changes in circuit optimization”, Proc. DAC ’04, pp. 438-441. • A. Mishchenko and R. Brayton, "SAT-based complete don't-care computation for network optimization", Proc. DATE '05, pp. 418-423. • K. McMillan, “Don't-care computation using k-clause approximation”, Proc. IWLS ’05, pp. 153-160. • Equivalence under don’t-cares • Q. Zhu, N. Kitchen, A. Kuehlmann, and A. L. Sangiovanni-Vincentelli. "SAT sweeping with local observability don't-cares," Proc. DAC ’06, pp. 229-234. • S. Plaza, K.-H. Chang, I. L. Markov, and V. Bertacco, “Node mergers in the presence of don't cares'', Proc. ASP-DAC’07, pp. 414-419. • Maximal reduction resynthesis without don’t-cares • K.-C. Chen and J. Cong, “Maximal reduction of lookup-table-based FPGAs”, Proc. DATE ’92, pp. 224-229. • Computing dependency functions using interpolation • C.-C. Lee, J.-H. R. Jiang, C.-Y. Huang, and A. Mishchenko. “Scalable exploration of functional dependency by interpolation and incremental SAT solving”, Proc. IWLS’07.

  23. Experimental Results • Implementation of SAT-based resynthesis • ABC: Logic synthesis and verification system developed at UC Berkeley • SAT solver used is MiniSat-C_v1.14.1 by Niklas Een and Niklas Sörensson • Outline of experiments • Perform technology-independent synthesis: resyn; if • Perform high-quality FPGA mapping: if • Perform resynthesis • without choices: imfs –W 66; imfs –a –W 66; imfs -W 66 • with choices (script is more complicated) • Measure gain in area, delay, net count • Commands used in the scripts • if is a new efficient FPGA mapper based on priority cuts • imfs is the new logic optimization and resynthesis engine described in the present paper, • resyn is a fast logic synthesis script that performs 5 iterations of AIG rewriting, • choice is a logic synthesis script that performs 15 passes of AIG rewriting and collects three snapshots of the current network: the original, the final, and an intermediate AIG saved after the first 5 rewriting passes. • Computer used • ? • Runtime is several minutes for the largest designs in the tables

  24. Academic Benchmarks

  25. Academic Benchmarks (PLAs)

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