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Chapter 11

Chapter 11. Logic Gate Circuitry. Basic Logic Families. TTL – transistor-transistor logic based on bipolar transistors. CMOS – complementary metal-oxide semiconductor logic based on metal-oxide-semiconductor field effect transistors (MOSFETs).

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Chapter 11

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  1. Chapter 11 Logic Gate Circuitry

  2. Basic Logic Families • TTL – transistor-transistor logic based on bipolar transistors. • CMOS – complementary metal-oxide semiconductor logic based on metal-oxide-semiconductor field effect transistors (MOSFETs). • ECL – emitter coupled logic based on bipolar transistors.

  3. General Characteristics of Basic Logic Families • CMOS consumes very little power, has excellent noise immunity, and is used with a wide range of voltages. • TTL can drive more current and uses more power than CMOS. • ECL is fast, with poor noise immunity and high power consumption.

  4. Logic Subfamilies • Both TTL and CMOS are available in a wide range of subfamilies. • In subfamilies, the part designations for identical logic functions remain the same, but the electrical characteristics are different.

  5. Examples of TTL Subfamilies

  6. Examples of CMOS Subfamilies

  7. Input/Output Voltage and Current Definitions • Values for any gate are designated with two subscripts: • The first subscript indicates an input or output value • The second subscript indicates the logic level

  8. Input/Output Voltage Designations • VOL – the logic LOW output voltage. • VOH – the logic HIGH output voltage. • VIL – the logic LOW input voltage. • VIH – the logic HIGH input voltage.

  9. Input/Output Voltage Designations

  10. Input/Output Current Designations • IOL – the logic LOW output current. • IOH – the logic HIGH output current. • IIL – the logic LOW input current. • IIH – the logic HIGH input current.

  11. Input/Output Current Designations

  12. Part Designation • Typically 54XXYY or 74XXYY. • 54 series is manufactured to military specifications. • 74 series is manufactured to commercial specifications. • XX is the subfamily designation. • YY is the part designation.

  13. Data Sheets • Use the appropriate maximum or minimum parameters in design. • Typical values should be considered “information only.” • Refer to Figure 11.3 in the textbook.

  14. Propagation Delay • The time required for the output of a digital circuit to change states after a change at one or more of its inputs. • Largely due to charging and discharging of capacitances inherent in the gate or flip-flop switching transistors.

  15. Propagation Delay Definitions • tpHL is the propagation delay when the device output changes from HIGH to LOW. • tpLH is the propagation delay when the device output changes from LOW to HIGH.

  16. Propagation Delay Definitions

  17. Propagation Delay Definitions

  18. Propagation Delay Factors • Varies with operating conditions. • Particularly affected by temperature and the power supply voltage.

  19. Propagation Delay of 74XX00 Gates

  20. Propagation Delay in Logic Circuits • Sum of the delays in the input-to-output paths. • Delays that do not affect the circuit output are ignored.

  21. Propagation Delay in Logic Circuits

  22. Input Data to Clock Timing • Setup time (tsu) – the time required for the synchronous inputs of a flip-flop to be stable before the clock active edge. • Hold time (th) – the time that the synchronous inputs of a flip-flop must remain stable after the clock active edge.

  23. Input Data to Clock Timing

  24. Clock Timing Requirement – 1 • Pulse width (tw) is the minimum time required for an active-level pulse applied to a input. • Values are measured from the midpoint of the leading edge of the pulse to the midpoint of the trailing edge.

  25. Clock Timing Requirement – 1

  26. Clock Timing Requirement – 2 • Recovery time (trec) is the time from the midpoint of the trailing edge of a pulse to the midpoint of an active edge CLK edge (See Table 11.4 in the textbook). • For a flip-flop, the propagation delay due to the clock is defined as the delay measured from the active edge of the clock to a corresponding change in Q.

  27. Clock Timing Requirement – 3

  28. Fanout • The number of gates that a logic gate is capable of driving without possible logic error. • Limited by the maximum current a gate can supply in a given logic state versus the current requirements of the load.

  29. Fanout Definitions • Driving gate is the gate whose output supplies current to the inputs of other gates. • Load gate is a gate whose input current is supplied by the output of another gate.

  30. Fanout Definitions

  31. Current Output Definitions • Sourcing means that the current flows out of the terminal. • Sinking means that the current flows into the terminal.

  32. Current Output Definitions

  33. Driving Gate Fanout • May be different for sourcing and sinking.

  34. Fanout Example for 74LS00 • IOL = 8 mAIIL = –0.4 mAnL = 20 • IOH = –0.4 mAIIH = 20 μAnH = 20

  35. Current Designations • Sourcing currents are designated as negative. • Sinking currents are designated as positive. • Sign is disregarded in fanout calculations.

  36. Exceeding Fanout • Output voltage VOL increases with increasing sink current. • Output voltage VOH decreases with increasing source current. • A greater load in either state takes the output voltage further away from its nominal value.

  37. Power Dissipation • The measure of energy used over time by electronic logic gates. • The product of the voltage and current required for the operation of the circuit.

  38. Power Dissipation in TTL Devices • PD = VCCICC. • VCC = power supply voltage. • ICC = current used. • In general, ICC = (ICCH + ICCL)/2.

  39. Power Dissipation in TTL Devices

  40. ICCL and ICCH • ICCL is the current drawn from the supply when all outputs are LOW. • ICCH the current drawn form from the supply when all outputs are HIGH.

  41. Power Dissipation in CMOS Devices • PD = VCCIT. • VCC = power supply voltage. • IT = quiescent + dynamic supply current.

  42. CMOS Quiescent vs. Dynamic Current • Quiescent current flows when the gate is in a steady state and is usually small. • Dynamic current flows when the gate is changing state. • The faster a CMOS gate switches, the more current (and the more power) it requires.

  43. Power Dissipation of TTL vs. CMOS • Power dissipation in TTL is independent of frequency. • Power dissipation in CMOS is dependent on frequency. • In slow circuits (< 1 MHz), CMOS is generally superior.

  44. Noise • Unwanted electrical signals. • Induced by electromagnetic fields by such sources as motors, fluorescent lights, high-frequency circuits, and cosmic rays. • Can cause erroneous operation of a digital circuit.

  45. Noise Margin • A certain amount of tolerance is built into digital devices to tolerate noise. • Noise margin is required for both LOW and HIGH inputs (See Figure 11.15 in the textbook).

  46. Noise Margin for 74LS04 • HIGH state:VNH = VOH – VIH = 3.0 V – 2.0 VVNH = 1.0 V. • LOW state:VNL = VIL – VOL = 0.8 V – 0.5 VVNL = 0.3 V.

  47. Noise Margin for 74HC00A • HIGH state:VNH = VOH – VIH = 3.98 V – 3.15 VVNH = 0.63 V. • LOW state:VNL = VIL – VOL = 1.35 V – 0.26 VVNL = 1.09 V.

  48. Interfacing TTL and CMOS • An extension of fanout and noise margin calculations. • Requires knowledge of input and output voltages and currents for the gates in question. • Refer to Table 11.5 in the textbook.

  49. High-Speed CMOS Driving 74LS • In general, the 74HC family satisfies the input voltage requirements of the 74LS family. • In general, the 74HC family can drive the 74LS family directly, with a fanout of 10.

  50. 74LS Driving 74HC • In general, the 74LS family satisfies the LOW-state criterion, but cannot guarantee sufficient output voltage in the HIGH state. • Requires a pull-up resistor on the output to ensure sufficient HIGH-state voltage at the 74HC input.

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