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CoolRunner™-II Advanced Features - II

CoolRunner™-II Advanced Features - II. Advanced CoolRunner-II Techniques-II. On the Fly Reconfiguration (OTF) Understanding OTF OTF Applications DataGATE Understanding DataGATE DataGATE Applications. On the Fly Reconfiguration (OTF). OTF exploits the RealDigital cell architecture

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CoolRunner™-II Advanced Features - II

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  1. CoolRunner™-II Advanced Features - II

  2. Advanced CoolRunner-II Techniques-II • On the Fly Reconfiguration (OTF) • Understanding OTF • OTF Applications • DataGATE • Understanding DataGATE • DataGATE Applications

  3. On the Fly Reconfiguration (OTF) • OTF exploits the RealDigital cell architecture • Initial pattern is loaded into a configuration shifter • The pattern first transfers into nonvolatile memory • The pattern is then read from NV to SRAM for actual cell operation • Leaves ability to reload the NV memory as we say, “On the Fly”

  4. CoolRunner-II High Level Architecture

  5. Behind the Scenes Configuration Memory

  6. Reconfiguration Process Nonvolatile Cell Volatile Cell

  7. Reconfiguration Process Blank Blank Initial Condition

  8. Reconfiguration Process Blank Pattern 1 Nonvolatile Programmed with Pattern 1

  9. Reconfiguration Process Pattern 1 Pattern 1 Both programmed with Pattern 1

  10. Reconfiguration Process Pattern 2 Pattern 1 Pattern 1 in Volatile Pattern 2 in Nonvolatile

  11. Reconfiguration Process Pattern 2 Pattern 2 Pattern 2 in Both

  12. WebPACK ISE5.2i Supports • iMPACT utility that permits OTF updates • User loads first pattern, then “inits” the part • Second pattern load occurs while first one runs • Init can be issued at any time the user wishes • After 50-100 microseconds, new pattern is running • Its that easy!

  13. iMPACT Menu

  14. Selecting the OTF

  15. OTF Applications • Uploading FPGA and changing function • Building small tables in Function Blocks • Changing PicoBlaze instructions • Changing keys on stream ciphers • Board level testing

  16. At power up CPLD configures FPGA (SelectMap JEDEC) FPGA active,CPU configures CPLD w. Interrupt JEDEC CPLD active, CPU configures CPLD w. SelectMap JEDEC System can be power cycled as needed FPGA CR-II FPGA Bitstream Select Map JTAG 3 SelectMap JEDEC CPU Interrupt JEDEC Configure FPGA then Handle Interrupts

  17. CoolRunner-II CPLD has multiple Function Blocks Each Function Block has Programmable Logic Array (PLA) PLA can also create “miniEPROM” or a table Can reprogram OTF Tables can hold constants, perform arithmetic, etc. FB FB FB FB AIM Small Tables

  18. Reloading an Instruction Set See PicoBlaze demonstration to see this in action!

  19. Encryption can be done with Linear Feedback Shift Registers (LFSR) Seed values and tap points can be changed OTF EX-OR Clear Bits to Encrypt Changing “key” can be done while the part operates Fancy LFSRs exist for better results (see Security presentation for detail) Encrypted Bits Q D LFSR Clear Bits Re-Keying a Stream Cipher

  20. Test patterns from CPLD drive/respond to other chips on board CPLD is updated via JTAG from off/on board CPU CPLD assumes different function when not testing board Board Testing PCB

  21. DataGATE • Initially defined as power saving feature • Block freely switching input signals • Can turn off clocks • Other applications arrived • Hot plugging • Debugging • Security

  22. DataGATE Assertion Rail

  23. DataGATEAssertion Rail Configuration Bit Data Latch InputPin to AIM DataGATE Input Pin Details

  24. DataGATE Timing

  25. Power Saving with External Pin Control DataGATE Assertion Rail AIM Signal drives low to pass data External signal drives high to enable data flow

  26. Using Internal Timer DataGATE Assertion Rail Timer Signal drives low to pass data External clock to internal timer

  27. Using State Machine Controller DataGATE Assertion Rail External clock Signal A Controller Signal drives low to pass data Signal B State Machine Inputs

  28. Hot Plugging with DataGATE Rack with Card Slots PCB with Logic DataGATE Switch & Light Electronics on card slots use CoolRunner-II with DataGate

  29. Debugging with DataGATE DataGATE Assertion Rail External clock Signal A Debug Trigger Signal drives low to pass data Signal B Debug Trigger Inputs

  30. Security with DataGATE DataGATE Assertion Rail External clock Password Password Checker Signal drives low to pass data PW Strobe Security Inputs

  31. Support • Standard WebPACK ISE 5.2 • CoolRunner-II Design Kit • More details for OTF in XAPP 388 • More details for DataGate in XAPP 395 • Additional advanced feature details in XAPP 378

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