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Status of Slave Board ( SLB ) ASIC

Status of Slave Board ( SLB ) ASIC. SLB ASIC (version 1) used in Slice Test 2001 has bugs in JTAG, Readout block (Parallel to Serial Converter: PSC). Timing instability of the long shift registers of PSC[218] and Control part (Mask[160] and Test Pulse[160])

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Status of Slave Board ( SLB ) ASIC

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  1. Status of Slave Board (SLB) ASIC • SLB ASIC (version 1) used in Slice Test 2001 has bugs in JTAG, Readout block (Parallel to Serial Converter: PSC). • Timing instability of the long shift registers of PSC[218] and Control part (Mask[160] and Test Pulse[160]) • Confliction of JTAG TDO data at the state transition from “shift” to “capture” DR due to timing problem • Bug fixed version SLB ASIC (version 2) has been delivered in July,2002 and tested since then. C.Fukunaga @ TGC electronics meeting in CERN

  2. Error phenomena • Shift register problem Frame Prev. BC data Current data Next data 2. JTAG state transition problem C.Fukunaga @ TGC electronics meeting in CERN

  3. Cure for the bugs • Introduction of Master-slave shift register structure • A small logic to ensure c(apture)DR must come later than TCK C.Fukunaga @ TGC electronics meeting in CERN

  4. Results C.Fukunaga @ TGC electronics meeting in CERN

  5. Name Bit RW DEPTH 21 RW Depth of L1 Buffer TESTPULSE 5 RW Set delay of Test Pulse Trigger DELAY 4 RW Set delay of input SCHEME 1 RW Low : 3 out-of 4 , High : 4 out-of 4 L1VETO 1 RW Low : through , High : L1A = 0 CLKINV 1 RW Low : order , High : invert RESET 1 RW Internal ECR & BCR DRDRST 1 RW Derandomizer Reset DCVETO 1 RW Low : DC balanced , High : Normal SEU 1 RO SEU Flag MODULE 8 RO Indicate Module Type and Module Address OVERFLOW 8 RO Indicate Derandomizer Overflow ID 32 RO ID=00100100000001001100000000000001 MASK1P 160 RW Mask Pattern for Readout and Matrix MASK1 160 RW Mask Enable for Readout and Matrix MASK2P 160 RW Mask Pattern for Matrix only MASK2 160 RW Mask Enable for Matrix only TPP 160 RW Test Pulse Pattern C.Fukunaga @ TGC electronics meeting in CERN

  6. Summary for SLB ASIC version 2 • Low-pT matrix part: Verification with 8000 patterns for each doublet/triplet and wire/strip. • Readout part: PSC with new shift register scheme works fine, but we are still doing tests for this parts. • Control part: All JTAG functions work fine. • Mask and Test Pulse: Both work fine owing to new shift register structure. C.Fukunaga @ TGC electronics meeting in CERN

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