0.25 micron Design Rules

1. 0.25 micronDesign Rules ECE 391 Northwestern University Last Updated: January 15, 2003

2. metal1 metal2 metal3 metal4 metal5 nwell pwell poly contact cp2m1 caa2m1 v23 v34 v45 aa (active area) nplus (select) pplus (select) CMOS Layers in Mentor Graphics 0.25 micron technology  L = 0.125 micron via (v12) ECE 391: 0.25 micron SCMOS Design Rules

3. contacts 2L 2L 2L 2L fixed 2L fixed 2L fixed contact contact_p2m1 contact_aa2m1 2L 2L 2L 2L contact with gate poly (i.e. poly over gate) contact_p2m1 with gate poly (i.e. poly over gate) contact_aa2m1 with gate poly (i.e. poly over gate) ECE 391: 0.25 micron SCMOS Design Rules

4. vias 4L 2L 3L 2L fixed via via spacing to active area via spacing to poly 3L 3L 3L via spacing to contact via spacing to contact_p2m1 via spacing to contact_aa2m1 3L 2L 2L fixed v23 v23 spacing to via 4L 4L 2L fixed 2L fixed v34 v45 ECE 391: 0.25 micron SCMOS Design Rules

5. active area 2L active area active area and poly 3L 3L 3L 3L contact contact_aa2m1 1L 1L active overlap with contacts 1L 1L ECE 391: 0.25 micron SCMOS Design Rules

6. nplus (select) nplus 2L 2L nplus overlap with contact in active area (active area hidden below nplus) 2L 2L nplus over active and gate poly (active area hidden below nplus) 2L 3L 3L 2L 2L nplus overlap with contact_aa2m1 in active area (active area hidden below nplus) nplus overlap with active area 2L 2L ECE 391: 0.25 micron SCMOS Design Rules

7. pplus (select) pplus 2L 2L 2L pplus overlap with contact in active area (active area hidden below pplus) 2L 2L 2L pplus over active and gate poly (active area hidden below pplus) 2L 3L 3L 2L 2L pplus overlap with contact_aa2m1 in active area (active area hidden below pplus) pplus overlap with active area 2L 2L ECE 391: 0.25 micron SCMOS Design Rules

8. nwell nwell to pwell nwell 9L 6L 10L 5L 5L 5L 5L distance from nwell boundary to pplus overlapping with active area distance from nwell boundary to nplus overlapping with active area ECE 391: 0.25 micron SCMOS Design Rules

9. pwell pwell to nwell pwell 9L 6L 10L 5L 5L 5L 5L distance from pwell boundary to pplus overlapping with active area distance from pwell boundary to nplus overlapping with active area ECE 391: 0.25 micron SCMOS Design Rules

10. poly poly spacing to active area poly 1L 2L 2L 2L poly and active area 3L 3L contact contact_p2m1 1L 1L poly overlap with contacts 1L 1L ECE 391: 0.25 micron SCMOS Design Rules

11. metal1 metal1 3L 3L contact contact_p2m1 1L 1L 1L 1L metal1 overlap with contacts and via contact_aa2m1 via 1L 1L 1L 1L ECE 391: 0.25 micron SCMOS Design Rules

12. metal5 4L 4L metal2-metal5 1L 1L metal2 overlap with vias metal2 4L via v23 4L 1L 1L 1L 1L metal3 overlap with via metal3 v23 v34 4L 4L 1L 1L metal4 overlap with via 1L 1L v45 metal4 v45 v34 4L 4L 1L 1L 1L metal5 overlap with via v45 1L ECE 391: 0.25 micron SCMOS Design Rules

13. n-type substrate (default) metal1 pplus select over active = p-type active layer active area (default: n-type) pplus select pwell nwell (substrate) tied to Vdd using this contact PMOS transistor poly NMOS transistor pwell tied to ground using this contact contact_aa2m1 Sample Layout: Inverter ECE 391: 0.25 micron SCMOS Design Rules