System synthesis and processor selection in the S 3 E 2 S environment

1. System synthesis and processor selection in the S3E2S environment Márcio Kreutz, Luigi Carro, Flávio Wagner, Marcio Oyamada SBCCI 99 Natal

2. 1 Outline • Introduction • Application and Processors characteristics • Processors selection • Case study • Conclusions

3. 2 • Specification, simulation and synthesis of embedded electronic systems • Distributed OO modeling • Whole system behaviour described • Granularity defined by user as C++ functions • Abstract behaviours • Decomposed into Digital Objects (DO) or Analogic Objects (AO). • DO mapped to processors Introduction

4. 3 Application Modeling SIMOO MET (Model Editor Tool)

5. 4 C++ function specification

6. 5 Application characterization • An application can be defined by its instructions types: • control jump, branch, conditional br.; • memory access load, store; and • processing operations add, or, mult

7. 6 Application characteristics • Type of data used • Size of required binary word • Maximum allowed execution time • Number of requested basic blocks (i.e., contiguous instructions without a branch) • Number of instructions in each basic block • Number of data points, and how they are stored • (local memory, register, large size memory) • Number of memory acc. in each basic block • Data dependencies

8. 7 Control: PPC = C C + M + P Memory: PPM = M C + M + P Processing: PPP = P C + M + P Functions mapping to processors • Application and Performance profiles • Processor characteristics testing according to the instructions types as:

9. 8 Processors characteristics • Size of binary word • Types of instructions • Memory operand accessing modes • Execution time of each instruction, in clock Cycles • Number of busses to access memory • Type of memory • Number of registers • Control instructions • Use of pipeline and depth of eventual pipeline • Use of harvard architecture or not

10. 9 Characteristics of tested Processors

11. 10 Processor selection block diagram Simulation SIMOO Classes Digital Objects Processors characteristics CDFG PP for each processor Mapping

12. 11 Processor selection • Processor library • each one with specific characterisitics • CISC, RISC, DSP, microcontrollers, ... • How does each processor execute a function behaviour ?? • Creation of a CDFG for all functions • to get the application and performance profiles

13. 12 PODOS integration CDFG Control Loop Acel_h Acel_v Acel_h Acel_v MUL MUL Int2 Int1 ADD Data flow Int3 CALL Vel_prev Vel1 ADD ATTRIB 2 Int4 DIV Vel_prev Int5 Tsampling Control MUL Processing mean ATTRIB Memory access vel

14. 13 Case study PODOS Integration algorithm for(int i; i < n; i++) { vel1= sqrt((acel_v*acel_v) + (acel_h*acel_h)); mean = (((vel_prev + vel1)/2) * Tsampling); vel_prev= vel1; vel = mean; }

15. 14 Case study PODOS Integration algorithm Memory accesses: 4 READ and 2 WRITE for(int i; i < n; i++) { vel1= sqrt((acel_v*acel_v) + (acel_h*acel_h)); mean = (((vel_prev + vel1)/2) * Tsampling); vel_prev= vel1; vel = mean; } Memory access cycles 8051 Risco C25 6 * 2 2 1 12 12 6 / 2 buses = 3

16. 15 Case study PODOS Integration algorithm 7 REG accesses for(int i; i < n; i++) { vel1= sqrt((acel_v*acel_v) + (acel_h*acel_h)); mean = (((vel_prev + vel1)/2) * Tsampling); vel_prev= vel1; vel = mean; }

17. 16 Case study PODOS Integration algorithm 3 MULT operation for(int i; i < n; i++) { vel1= sqrt((acel_v*acel_v) + (acel_h*acel_h)); mean = (((vel_prev + vel1)/2) * Tsampling); vel_prev= vel1; vel = mean; } Processing cycles 8051 Risco C25 3 * 48 1 1 96 3 3

18. 17 Case study PODOS Integration algorithm 1 DIV operation for(int i; i < n; i++) { vel1= sqrt((acel_v*acel_v) + (acel_h*acel_h)); mean = (((vel_prev + vel1) / 2) * Tsampling); vel_prev= vel1; vel = mean; } Processing cycles 8051 Risco C25 1* 48 1 1 48 1 1

19. 18 Case study PODOS Integration algorithm 3 ADDs for(int i; i < n; i++) { vel1= sqrt((acel_v*acel_v) + (acel_h*acel_h)); mean = (((vel_prev + vel1)/2) * Tsampling); vel_prev= vel1; vel = mean; } Processing cycles 8051 Risco C25 3* 3 1 1 9 3 3

20. 19 Case study PODOS Integration algorithm 2 ATTRIB for(int i; i < n; i++) { vel1= sqrt((acel_v*acel_v) + (acel_h*acel_h)); mean = (((vel_prev + vel1)/2) * Tsampling); vel_prev= vel1; vel = mean; } Processing cycles 8051 Risco C25 2* 3 1 1 6 2 2

21. 20 Case study PODOS Integration algorithm 2 Control operations for(int i; i < n; i++) { vel1= sqrt((acel_v*acel_v) + (acel_h*acel_h)); mean = (((vel_prev + vel1)/2) * Tsampling); vel_prev= vel1; vel = mean; } Control cycles 8051 Risco C25 2* 3 1 4 6 2 8

22. Podos Integration results 21 Performance Profiles

23. Digital Filter results 22 Performance Profiles

24. Dot Product Results 23 Performance Profiles

25. 24 Conclusions • Synthesis based on a library of processors • Exploration of the characteristics of all • function presented in application • Mapping to processors made through • processors characteristics • multiprocessor system

26. 25 Future works • Distributed protocol selection and • synthesis • Merge objects in processors • Code generation • SIMOO MET integration