VHDL Project II: Array Multiplier

1. VHDL Project II:Array Multiplier Slides Available at: www.pages.drexel.edu/~mjm46 Matthew Murach

2. Today’s Agenda • Finish up the processing element design • Work on array multiplier design/layout • Today’s quiz will be given in the last 30 minutes of the lab period. The quiz is timed and all quizzes will be collected at 11:00 am.

3. Recall from last time… • The array multiplier that we are designing involves the use of processing elements (PE) to breakdown the task of multiplying an n-bit vector by a n-bit vector. • Using a serial approach much like the adder project the operation should take roughly ~n operations (slight larger) • To design a high performance multiplier we can perform some operations in parallel rather then in serial.

4. Array Multiplier Layout 4x4 A(3) A(2) A(1) A(0) B(0) F(0) B(1) F(1) B(2) F(2) B(3) F(3) F(7) F(6) F(5) F(4)

5. Sample Run Say we have, 1010 x1001 0000 + 1010 1010 1010 x1001 0101 +0000 0101 1010 x1001 0010 +0000 0010 1010 x1001 0001 +1010 1011 Partial Sum 1st bit of answer 2nd bit of answer 3rd bit of answer The rest of the answer 1011010 = 90 Verify!

6. For-if generation constructs • Elements can be easily duplicated in a design using for-if-generate notation. • The syntax for this arrangement is shown below Gen_name_0 : For i in 0 to N-1 generate gen_name_1 : if(condition) generate cell : component_name port map (stuff); end generate gen_name; gen_name_2 : if (condition) generate cell : component_name port map (stuff); end generate gen_name_2; End generate gen_name_0; • Note that generate statements go after the first begin.

7. Example Super Buffer -- Example of cell Entity of PE is Port(A : in std_logic; B : out std_logic); End PE; Architecture Behav of PE is Begin Process(A) Begin B <= not A; End process; End Behav; -- Example of Cell Generation Library IEEE; Use ieee.std_logic_1164.all; Entity of sbuf is Port( A : in std_logic Z : out std_logic); End sbuf; Architecture Behav of Buffer is Component PE Port(A : in std_logic; B : out std_logic); End component; -- Signal Declarations Signal x : std_logic_vector(4 downto 0); Begin -- Port Map section GI : for i in 0 to 5 Generate G1 : if (I = 0) generate -- 1st generate Cell : PE port map(A, x(i)); End generate G1; G2 : if (I < 5 and I > 0) generate -- 2nd generate Cell : PE port map( x(I-1),x(I)); End generate G2; G3 : if (I = 5) generate Cell : PE port map (x(I-1),Z); -- 3rd generate End generate G3; End generate GI; End Behav; What in the world does this synthesize to ? See the Next Slide for Details 

8. For I in 0 to 5 generate X(0) X(1) X(2) X(3) X(4) Cell:0 Cell:1 Cell:2 Cell:3 Cell:4 Cell:5 I=0 I=1 I=2 I=3 I=4 I=5 A Z Synthesis Results • Red circle denotes region G1 • Yellow circles denote region G2 • Green circle denotes region G3 • Green arrows indicate A • Red arrows indicate -A

9. Array Multiplier Layout 4x4 A(3) A(2) A(1) A(0) B(0) F(0) B(1) F(1) B(2) F(2) B(3) F(3) F(7) F(6) F(5) F(4)

10. Array Multiplier Architecture behav of Array_Mult is -- Define Signals Here -- Define your PE component Begin -- Declare boundary conditions using for-generate GI : for i in 0 to N-1 Generate GJ : for j in 0 to N-1 Generate -- Subclasses of networks inside multiplier -- Top or middle nodes G1 : if (i < N-1) and (j < N-1) and (j > 0) Generate cell : PE port map (x(i,j),y(i,j),c(i,j),p(i,j), x(i+1,j),y(i,j+1),c(i,j+1),p(i+1,j-1)); End Generate G1; -- Fill in the other four sections here End Generate GJ; End Generate GI; End behav;

11. Project Guidelines • Teams: It is suggested that you should work in groups of two on this assignment. • Reports should be 2~3 pages in length and have all the source code included. Email or Paper submittal is acceptable. E-mail is the preferred submission method • Reports submitted should detail the methodology used to obtain the final work. • All code submitted should be well commented and should follow good coding guidelines. • The deadline for this project April 27th Tuesday @ 11:59:59 pm