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Intro to VHDL

Appendix A: page 779 - page 831. Intro to VHDL. VHDL is an IEEE and ANSI standard. VHDL stands for Very High Speed IC hardware description language . VHDL supports A wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions.

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Intro to VHDL

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  1. Appendix A: page 779 - page 831 Intro to VHDL

  2. VHDL is an IEEE and ANSI standard. • VHDL stands for Very High Speed IC hardware description language. • VHDL supports • A wide range of abstraction levels ranging from abstract behavioral descriptions to very precise gate-level descriptions. • Synchronous and asynchronous timing models. • Three different description styles: structural, data-flow, and behavioral.

  3. Documentation in VHDL Code • Two characters – denote the beginning of the comments • VHDL ignore any text on the line after – • Data Objects • Names, values and numbers, Signal • SINGAL signal_name : type_name; • Operators : Precedence • Design entity • Package • Using sub-circuits • Current assignments • Sequential assignments

  4. Three Basic Data objects in VHDL • SIGNAL • the most important data objects, which represent the logic signals (wires) in the circuit. • CONSTANT • VARIABLE

  5. A.2 SIGNAL is the most important data object in VHDL • A signal must be declared with a type as SIGNAL signal_name : type_name; • 10 signal types: BIT, BIT_VECTOR, STD_LOGIC, STD_LOGIC_VECTOR, STD_ULOGIC, SIGNED, UNSIGNED, INTEGER, ENUMERATION, BOOLEAN.

  6. BIT and BIT_VECTOR • Objects of BIT type can only have the values ‘0’ or ‘1’. • An object of BIT_VECTOR type is a linear array of BIT objects. SIGNAL x1 : BIT; SIGNAL C : BIT_VECTOR (1 TO 4); SIGNAL Byte: BIT_VECTOR (7 DOWNTO 0); C <= “1010”; -- results in C(1) = 1, C(2) = 0, C(3) = 1, C(4) = 0

  7. STD_LOGIC and STD_LOGIC_VECTOR • STD_LOGIC provides more flexibility than the BIT type. To use this type, must include LIBRARY ieee; USE ieee.std_logic_1164.all; Legal values for a STD_LOGIC data objects: 0, 1, Z , - Z – high impedance ‘-’ – ‘don’t care’

  8. A.3 VHDL Operators • VHDL standard groups all operators into formal classes. • Operators in a given class have the same precedence. • Operators of the same class are evaluated from left to right. • Parenthesis should be used to ensure the correct interpretation of the expression. • x1 AND x2 OR x3 AND x4 = • (x1 AND x2) OR (x3 AND x4)

  9. Table A.1. The VHDL operators.

  10. A.4 VHDL Design entity Figure A.1. The general structure of a VHDL design entity.

  11. x 1 x 2 f x 3 Figure 2.30. A simple logic function.

  12. A4.1 Entity declaration describes the external view of the entity. • ENTITY example1 IS • PORT ( x1, x2, x3 : INBIT ; • f : OUTBIT ) ; • ENDexample1; • /* declare signals In an entity declaration */ Figure 2.31. VHDL entity declaration for the circuit in Figure 2.30.

  13. A4.2 Architecture body contains the internal description of the entity.

  14. ARCHITECTURELogicFunc OF example1 IS • BEGIN • f <= (x1 AND x2) OR (NOT x2 AND x3) ; • ENDLogicFunc ; • /* A set of concurrent or sequential statements that represents the behavior of the entity.*/ Figure 2.32. VHDL architecture for the entity in Figure 2.31.

  15. Figure 2.33. Complete VHDL code for the circuit in Figure 2.30.

  16. ENTITY example2 IS PORT(x1, x2, x3, x4 : IN BIT; f, g : OUT BIT); END example2; ARCHITECTURE LogicFunc OF example2 IS BEGIN f <= (x1 AND x2) OR (x2 AND x4); g <= (x1 OR (NOT x3)) AND ((NOT x2) OR x4); END LogicFunc;

  17. ENTITY example2 IS PORT(x1, x2, x3, x4 : IN BIT; f, g : OUT BIT); END example2; ARCHITECTURE LogicFunc OF example2 IS BEGIN f <= (x1 AND x2) OR (x2 AND x4); g <= (x1 OR (NOT x3)) AND ((NOT x2) OR x4); END LogicFunc;

  18. ENTITY example2 IS PORT(x1, x2, x3, x4 : IN BIT; f, g : OUT BIT); END example2; ARCHITECTURE LogicFunc OF example2 IS BEGIN f <= (x1 AND x2) OR (x2 AND x4); g <= (x1 OR (NOT x3)) AND ((NOT x2) OR x4); END LogicFunc;

  19. A.6 Using sub-circuits • An entity X, when used in another entity Y, is called component X.- A component is also an entity.

  20. w1 x1 in1 g f out in2 w2 x2 in3 h w3 x3 B A w4 in4 in5

  21. Architecture body consists of a set of interconnected components that represents the structure of the entity. ENTITY part3 IS PORT(in1, in2, in3, in4, in5 : IN BIT; out : OUT BIT); END part3; ARCHITECTURE Structure OF part3 IS COMPONENT A PORT(x1, x2, x3 : IN BIT; f : OUT BIT); END COMPONENT; COMPONENTB PORT(w1, w2, w3, w4 : IN BIT; g, h : OUT BIT); END COMPONENT; SINGAL g, h : BIT; BEGIN instB : B PORT MAP (in1, in2, in3, in4, g, h); instA: A PORT MAP (g, in5, h, out); END Structure;

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