1 / 19

SRAM DESIGN PROJECT PHASE 2

SRAM DESIGN PROJECT PHASE 2. Nirav Desai 4280229 VLSI DESIGN 2: Prof. Kia Bazargan Dept. of ECE College of Science and Engineering University of Minnesota, Twin Cities. University of Minnesota. SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE

andra
Download Presentation

SRAM DESIGN PROJECT PHASE 2

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. SRAM DESIGN PROJECT PHASE 2 Nirav Desai 4280229 VLSI DESIGN 2: Prof. Kia Bazargan Dept. of ECE College of Science and Engineering University of Minnesota, Twin Cities University of Minnesota

  2. SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE • NMOS inverter = 110nM PMOS inverter = 220nM NMOS Access = 90nM • NMOSinv/NMOSaccess = 1.2 PMOSinv/NMOSaccess=2.4 • Cbitline = 0.747fF for 512 cell array ( Interconnect Parasitics from ASU PTM Website ) University of Minnesota

  3. SRAM CELL READ AND WRITE MARGIN FROM BUTTERFLY CURVE • NMOS inverter = 150nM PMOS inverter = 555nM NMOS Access = 180nM • NMOSinv/NMOSaccess = 1.2 PMOSinv/NMOSaccess = 3 Cbitline = 0.747fF • Curve shows SRAM cell is close to write failure. • BitlinePrecharge to less than 1.1V could be explored to increase SNM. University of Minnesota

  4. Simulation Setup V(word) V(ic) V(write) V(bit) V(bitbar) V(qbar) V(q) • M0,M1,M3,M4 form the cross coupled inverter pair • M5,M6 are access transistors • C1, C2 is the bitline capacitance • M7 is the precharge switch for bitline ( bit ) - V3 precharges the bitline to 0.8V • V6 prechargesbitbar and writes a 0 to the cell University of Minnesota

  5. Timing Waveforms for Characterization V(write) – Applied to source of M7 (precharge switch) • V(write) prechargesCbit to 0.8V via M7 • V(word) disables access transistors • M5 and M6 during precharge . • V(qbar) and V(q) are used to generate • the butterfly curves. • V(ic) enables M7 during precharge • It could be implemented as NOT(V(word)). • V(bitbar) precharges to 0.8V, shows charge pumping when M7 turns off and follows V(qbar) when wordline is enabled. • V(bit) follows V(q) after word line is • enabled. • V(bit) precharged to Vdd by V6 V(word) – Wordline Voltage V(qbar) V(q) V(ic) – Enables the precharge switch M7 V(bitbar) V(bit) University of Minnesota

  6. PASS TRANSISTOR BASED TREE DESIGN 1:8 Row Decoder Tree a1 a2 a2 a0 a2 a1 a2 8 MSB BUFFERS in a2 a1 a2 a0 a1 a2 a2 Similar Tree Decoder for 16 LSB Bits University of Minnesota

  7. TREE DECODER DESIGN 23= 8 MSB Bits for Word Line Address from Row Buffers Directions of Increasing bit number 24 = 16 LSB Bits for Word Line Address from Column Buffers From row buffer To Word Line Buffer From column buffer University of Minnesota

  8. PASS TRANSISTOR BASED TREE DESIGN CK OUT IN CK Identical Sizing for NMOS and PMOS to minimize charge injection effects • Delay drops by ~40ps/2 for every • Doubling of transistor widths • Delay drop saturates around • 1000nM to 89ps • Used W/L of 880/50 for final tree University of Minnesota

  9. TREE DECODER TIMING DIAGRAMS The following waveforms were applied to the row and column selection inputs of the tree decoder University of Minnesota

  10. TREE DECODER TIMING DIAGRAMS It takes one cycle for initializing the tree decoder after which we get clean pulses for each row output LSB pulse is wider than MSB pulse in bottom figure to allow the tree to clear present state before next University of Minnesota

  11. TREE DECODER TIMING DIAGRAMS The top waveforms shows the matrix point output where the row and column select inputs are high The output node discharges when the input goes low University of Minnesota

  12. SRAM TIMING CIRCUIT Timing Sequence: Disconnect Precharge Enable Word Line SAE / Write Enable Wait for read/write Disble SAE/Write Enable Disable Wordline Reconnect Precharge and discharge all word lines SAE/Write Enable in Precharge Wordline Enable Read/Write Input Pulse Precharge Disable Pulse Word Line Enable Pulse Read/Write Output Pulse University of Minnesota

  13. SRAM TIMING INTEGRATION CIRCUIT 2 copies of timing circuit from previous slide for read and write Pass Transistors are used for combining the Wordline and Precharge Signals from Read and Write instructions or1 Sense Amplifier Enable Wordline Precharge Read Bit Predischarge Transistor for Output Node when no Signal at the input or2 Write Bit Write Driver Enable (WE) Wordline Precharge OUT Same circuit as above right or1 or2 or2 or1 University of Minnesota

  14. READ WRITE CIRCUIT ( Design by Bong Jin ) Write Driver Sense Amplifier Precharge Circuit University of Minnesota

  15. READ WRITE CIRCUIT TEST SETUP Single SRAM Cell for simulations Cbitestimate for 512 rows NMOS Switches to allow read without disabling write circuit Bitline Capacitance estimate from ASU PTM Website University of Minnesota

  16. READ / WRITE TIMING WAVEFORMS Precharge Pulse ( Active Low ) Data Meant to be written to cell Write Enable Pulse Read Enable Pulse Output of Write Buffer Disable output buffer ( tristate logic ) Bitline Bitline Bar Data Output Data Out Bar University of Minnesota

  17. SRAM Cell Layout University of Minnesota

  18. 4X4 SRAM Array Layout This unit can be replicated in all directions without any changes. LVS check remaining Array Size = 3.7975umX2.4725um B0 B0BAR B1 B1BAR GND WORD 1 VDD WORD 0 GND University of Minnesota

  19. References • Digital Integrated Circuits Jan Rabaey, AnanthaChandrakasan, BorivojeNikolic ( SRAM Cell Design, Decoders, Read Write Circuits ) • CMOS VLSI Design by Weste and Harris ( Butterfly Curves ) • CMOS Circuit Design, Layout and Simulation Baker, Li, Boyce (Decoder Design) • Course slides of Prof. Kia Bazargan ( Precharge Techniques, Decoders, SRAM Cell Design ) University of Minnesota

More Related