EES: Burn – in test

1. EES: Burn – in test Eliminate infant mortality: Not possible to detect it with AOI, FPT, X-ray or ICT!

2. EES: Burn – in test Preliminary version already defined: * Previous experience from AUGER and ANTARES • A first cold cycle with 10 minutes dwell time at 0ºC • 16 hours burn-in at 70 °C • More or less 10 cycles with 5°C / minutes ( -0 to +70°C) fall and rise time and 10 minutes dwell time • Maximum temperature : 70°C (or maximum specified components temperature) • Minimum temperature : 0°C (or minimum specified components temperature) • The board should be ON and a minimum functional test should be performed if possible (using caps and loops on input/output ports and serial bus like Ethernet or RS232… for communication with board inside oven) • Make a 5 minutes Power Off during minimum and maximum dwell time of the penultimate cycle • To be use as reference: the test can be adapted to the needs of each board

3. Burn-in Test: Dew Temperature Relative humidity The following formula was proposed in a 2005 article by Mark G. Lawrence in the Bulletin of the American Meteorological Society: Tdew= T - ((100 - RH)/5) RH = 30 % -> Tdew= 14 º smallerthanambiencetemperature. Goodenough? RH = 40 % -> Tdew = 12 º

4. ProductionStrategy: • CLBv2: • Manufacturer: AOI + x-ray BGA components + functionaltests (tender close) • KM3NeT: Burn-in tests + secondfunctional test (Withthe PB) ??? • (possibilitytooutsourcethem – no PON money) • PBv2: • Manufacturer: ? • KM3NeT: ? • PMT BASES: • Manufacturer: Tender specificationsbeingfinished: Probably AOI + SystemOn Chip . • KM3NeT: Functional test ontheintegrationtests. EES notclearyet. • Octopusv3: • Manufacturer: ( AOI + functional test + EES + functional test) ? • KM3NeT: Nothing ? (Ideal scenario!) • Nanobeacon: • Manufacturer: (AOI + functional test + EES + functional test) • KM3NeT: Nothing? (ideal scenario!)

5. CLBv2 + PBv2 burn-in test: • Togetheris simple tosupplythem • (Onlytwo cables) • Powersupplywithenouthcurrentneededorseveralused (To be Study) • In test measurementsusing USB UART + USB driver expansorconnectedtoonecomputer. Software needed-> Notnow, in October • Number of board per EES to be determined: • 20 a goodnumber • 600 / 20 = 30 cycles • 3 cycles per week -> 3 DU per week

6. PBv2 modifications: • - Remove inter rail diodes • - Add Schmitt trigger to add hysteresis to the start-up/down of the DC/DCs. • 11V on / 9V off -> Already know the values? Tested with a slow power supply? • - Still needed clarification from Rossana about the protections at the 400V/12V DC/DC converter …. Probablythey are alreadythere, so notneeded at the PBv2 • - Use of zener at the output rails? Notneeded? • Xilinx response to the current power-down sequence of the KINTEX: • “our position is that if the customer powers the device down out of order then there is a risk that the IOs can glitch since the supplies powering them are still active • As long as the customer is happy to live with this risk (i.e. everything is powering down and a glitch on the IO pins won't matter) then he should be ok to proceed” • The question is: Can an IO glitch at the shut-down damage some DOM device? • Current in-rushcurrent: • Whatisthecurrentvalue (withouttheinterraildiodes)? -> Rossana willneedit in order to fixtheprotections at the 400/12 DC/DC output

7. Octopusv3 + PMT bases tests: • Connectone PMT base toone Octopusv3 prototype and plugittothe CLB prototype -> Test I2C communicationstothe PMT base • Validate Octopusv3 protos • On-shore station: • Nextweeksetting in the IFIC thebroadcast “proof of concept” test benchdevelopedby 7S: • 3 WR switches • 2 Specs • Wewill try alsoto test itwithone CLBv2 prototype • CLBv2 + PBv2.2next prototype • 7 CLBv2 prototypesalreadyorderedto MASER • 5 PBv2 to be orderedthisweek

8. DFX analysis: • Price quotationbeingpreparedby TBP for Octopusv3, CLBv2 and PBv2. • ODB++ files from CLBv2 needed. • Highly Accelerated Stress Testing: • Can help to find weak points. • To be applied to only one of the current prototypes once there are available more boards of next series. • CLB+PB can be tested together • Octopusv3 • PMT Base -> can be done already? • To be defined: 10 cycles of temperature – visual inspection +functional test – 10 cycles of temperature with 5ºC more in the upper limit (and 5 less in the inferior one) …. Untilthefirst mal functioningontheboardappears • EMI tests • Status? • Lead: • Remember, it can be usedin thesoldering and givesbetterreliability.

9. Software for data Analysis (contributionfromoutsidetheelectronicsgroup): • Alex: JPP data analysis software (Thesameoneusedforthe PPM DOM data analysis– CLBv1) • Carmelo: UDP server for CLBv2 frames • SPI: neededtoimplementtheimageswrittingonthe flash • PatterngeneratorforthePseudo-Octopus: Implementationonthe KC705 ongoing • System test: • - Firmware integration in progress • - Spec as WR master and as opticalethernetcardready in a linux machine • Meeting of Bologna: • FIDES resultreview: CLBv2, PBv2, Octopusv3 and PMT bases • Review of the CLBv2, PBv2 and Octopusv3 modificationsforthenextProtoiteration • Preparation of theproduction: • Use of ESS • Planification