1 / 53

Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University

ELEC 7770 Advanced VLSI Design Spring 2014 Linear Programming – A Mathematical Optimization Technique. Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu

ann-lamb
Download Presentation

Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ELEC 7770Advanced VLSI DesignSpring 2014 Linear Programming – A Mathematical Optimization Technique Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14/course.html ELEC 7770: Advanced VLSI Design (Agrawal)

  2. What is Linear Programming • Linear programming (LP) is a mathematical method for selecting the best solution from the available solutions of a problem. • Method: • State the problem and define variables whose values will be determined. • Develop a linear programming model: • Write the problem as an optimization formula (a linear expression to be minimized or maximized) • Write a set of linear constraints • An available LP solver (computer program) gives the values of variables. ELEC 7770: Advanced VLSI Design (Agrawal)

  3. Types of LPs • LP – all variables are real. • ILP – all variables are integers. • MILP – some variables are integers, others are real. • A reference: • S. I. Gass, An Illustrated Guide to Linear Programming, New York: Dover, 1990. ELEC 7770: Advanced VLSI Design (Agrawal)

  4. A Single-Variable Problem • Consider variable x • Problem: find the maximum value of x subject to constraint, 0 ≤ x ≤ 15. • Solution: x = 15. Constraint satisfied x 15 0 Solution x = 15 ELEC 7770: Advanced VLSI Design (Agrawal)

  5. Single Variable Problem (Cont.) • Consider more complex constraints: • Maximize x, subject to following constraints: • x ≥ 0 (1) • 5x ≤ 75 (2) • 6x ≤ 30 (3) • x ≤ 10 (4) 0 5 10 15 x (1) (2) (3) (4) All constraints satisfied Solution, x = 5 ELEC 7770: Advanced VLSI Design (Agrawal)

  6. A Two-Variable Problem • Manufacture of chairs and tables: • Resources available: • Material: 400 boards of wood • Labor: 450 man-hours • Profit: • Chair: $45 • Table: $80 • Resources needed: • Chair • 5 boards of wood • 10 man-hours • Table • 20 boards of wood • 15 man-hours • Problem: How many chairs and how many tables should be manufactured to maximize the total profit? ELEC 7770: Advanced VLSI Design (Agrawal)

  7. Formulating Two-Variable Problem • Manufacture x1 chairs and x2 tables to maximize profit: P = 45x1 + 80x2 dollars • Subject to given resource constraints: • 400 boards of wood, 5x1 + 20x2 ≤ 400 (1) • 450 man-hours of labor, 10x1 + 15x2 ≤ 450 (2) • x1 ≥ 0 (3) • x2 ≥ 0 (4) ELEC 7770: Advanced VLSI Design (Agrawal)

  8. Solution: Two-Variable Problem 40 30 20 10 0 P = 2200 Best solution: 24 chairs, 14 tables Profit = 45×24 + 80×14 = 2200 dollars Man-power constraint (1) Tables, x2 (24, 14) Material constraint (3) P = 0 (4) 0 10 20 30 40 50 60 70 80 90 Chairs, x1 increasing (2) Profit decresing ELEC 7770: Advanced VLSI Design (Agrawal)

  9. Change Profit of Chair to $64/Unit • Manufacture x1 chairs and x2 tables to maximize profit: P = 64x1 + 80x2 dollars • Subject to given resource constraints: • 400 boards of wood, 5x1 + 20x2 ≤ 400 (1) • 450 man-hours of labor, 10x1 + 15x2 ≤ 450 (2) • x1 ≥ 0 (3) • x2 ≥ 0 (4) ELEC 7770: Advanced VLSI Design (Agrawal)

  10. Solution: $64 Profit/Chair P = 2880 40 30 20 10 0 Best solution: 45 chairs, 0 tables Profit = 64×45 + 80×0 = 2880 dollars Man-power constraint (1) Tables, x2 (24, 14) Material constraint (3) P = 0 (4) 0 10 20 30 40 50 60 70 80 90 Chairs, x1 (2) increasing Profit decresing ELEC 7770: Advanced VLSI Design (Agrawal)

  11. A Dual Problem • Explore an alternative. • Questions: • Should we make tables and chairs? • Or, auction off the available resources? • To answer this question we need to know: • What is the minimum price for the resources that will provide us with same amount of revenue from sale as the profits from tables and chairs? • This is the dual of the original problem. ELEC 7770: Advanced VLSI Design (Agrawal)

  12. Formulating the Dual Problem • Revenue received by selling off resources: • For each board, w1 • For each man-hour, w2 • Minimize 400w1 + 450w2 • Subject to constraints: • 5w1 + 10w2 ≥ 45 • 20w1 + 15w2 ≥ 80 • w1 ≥ 0 • w2 ≥ 0 Resources: Material: 400 boards Labor: 450 man-hrs Profit: Chair: $45 Table: $80 Resources needed: Chair 5 boards of wood 10 man-hours Table 20 boards of wood 15 man-hours ELEC 7770: Advanced VLSI Design (Agrawal)

  13. The Duality Theorem • If the primal has a finite optimum solution, so does the dual, and the optimum values of the objective functions are equal. • Reference: G. Strang, Linear Algebra and Its Applications. Fort Worth: Harcourt Brace Javanovich College Publishers, third edition, 1988. ELEC 7770: Advanced VLSI Design (Agrawal)

  14. Primal problem Fixed resources Maximize profit Variables: x1 (number of chairs) x2 (number of tables) Maximize profit 45x1+80x2 Subject to: 5x1 + 20x2 ≤ 400 10x1 + 15x2 ≤ 450 x1 ≥ 0 x2 ≥ 0 Solution: x1 = 24 chairs, x2 = 14 tables Profit = $2200 Dual Problem Fixed profit Minimize value Variables: w1 ($ value/board of wood) w2 ($ value/man-hour) Minimize value 400w1+450w2 Subject to: 5w1 + 10w2 ≥ 45 20w1 + 15w2 ≥ 80 w1 ≥ 0 w2 ≥ 0 Solution: w1 = $1, w2 = $4 value = $2200 Primal-Dual Problems ELEC 7770: Advanced VLSI Design (Agrawal)

  15. LP for n Variables n minimize Σcj xj Objective function j =1 n subject to Σaij xj ≤ bi,i = 1, 2, . . ., m j =1 n Σcij xj = di,i = 1, 2, . . ., p j =1 Variables: xj Constants: cj, aij, bi, cij, di ELEC 7770: Advanced VLSI Design (Agrawal)

  16. Algorithms for Solving LP • Simplex method • G. B. Dantzig, Linear Programming and Extension, Princeton, New Jersey, Princeton University Press, 1963. • Ellipsoid method • L. G. Khachiyan, “A Polynomial Algorithm for Linear Programming,” Soviet Math. Dokl., vol. 20, pp. 191-194, 1984. • Interior-point method • N. K. Karmarkar, “A New Polynomial-Time Algorithm for Linear Programming,” Combinatorica, vol. 4, pp. 373-395, 1984. • Course website of Prof. Lieven Vandenberghe (UCLA), http://www.ee.ucla.edu/ee236a/ee236a.html ELEC 7770: Advanced VLSI Design (Agrawal)

  17. Basic Ideas of Solution methods Extreme points Extreme points Objective function Objective function Constraints Constraints Simplex: search on extreme points. Complexity: polynomial in n, number of variables Interior-point methods: Successively iterate with interior spaces of analytic convex boundaries. Complexity: O(n3.5L), L = no. of int. values ELEC 7770: Advanced VLSI Design (Agrawal)

  18. Integer Linear Programming (ILP) • Variables are integers. • Complexity is exponential – higher than LP. • LP relaxation • Convert all variables to real, preserve ranges. • LP solution provides guidance. • Rounding LP solution can provide a non-optimal solution. ELEC 7770: Advanced VLSI Design (Agrawal)

  19. Traveling Salesperson Problem (TSP) 4 6 12 5 27 1 12 18 15 20 19 10 2 3 5 ELEC 7770: Advanced VLSI Design (Agrawal)

  20. Solving TSP: Five Cities Distances (dij) in miles (symmetric TSP, general TSP is asymmetric) ELEC 7770: Advanced VLSI Design (Agrawal)

  21. Search Space: No. of Tours • Asymmetric TSP tours • Five-city problem: 4 × 3 × 2 × 1 = 24 tours • Ten-city problem: 362,880 tours • 15-city problem: 87,178,291,200 tours • 50-city problem: 49! = 6.08×1062 tours Time for enumerative search assuming 1 μs per tour evaluation = 1.93×1055 years ELEC 7770: Advanced VLSI Design (Agrawal)

  22. A Greedy Heuristic Solution Tour length = 10 + 5 + 12 + 6 + 27 = 60 miles (non-optimal) ELEC 7770: Advanced VLSI Design (Agrawal)

  23. ILP Variables, Constants and Constraints 4 x14 ε [0,1] d14 = 12 5 x15 ε [0,1] 1 d15 = 27 Integer variables: xij = 1, travel i to j xij = 0, do not travel i to j Real constants: dij = distance from i to j x12 ε [0,1] d12 = 18 x13 ε [0,1] d13 = 10 2 3 x12 + x13 + x14 + x15 = 1 four other similar equations ELEC 7770: Advanced VLSI Design (Agrawal)

  24. Objective Function and ILP Solution 5 i - 1 Minimize ∑ ∑ xij × dij i = 1 j = 1 ∑ xij = 1 and xii = 0 for all i j ≠ i ELEC 7770: Advanced VLSI Design (Agrawal)

  25. ILP Solution d54 = 6 4 5 d45 = 6 1 d21 = 18 d13 = 10 2 3 d32 = 5 Total length = 45 but not a single tour ELEC 7770: Advanced VLSI Design (Agrawal)

  26. Additional Constraints for Single Tour • Following constraints prevent split tours. For any subset S of cities, the tour must enter and exit that subset: ∑ xij ≥ 2 for all S, |S| < 5 i ε S j ε S Remaining set At least two arrows must cross this boundary. Any subset ELEC 7770: Advanced VLSI Design (Agrawal)

  27. ILP Solution 4 d54 = 6 d41 = 12 5 1 d25 = 20 d13 = 10 2 3 d32 = 5 Total length = 53 ELEC 7770: Advanced VLSI Design (Agrawal)

  28. ILP Example: Test Minimization • A combinational circuit has n test vectors that detect m faults. Each vector detects a subset of faults. Find the smallest subset of test vectors such that each fault is detected by at least N vectors. • Simulate vectors without dropping faults. Test vectors fij = 1, if test Ti detects fault Fj Faults ELEC 7770: Advanced VLSI Design (Agrawal)

  29. Test Minimization by ILP • Construct an ILP model: • Assign an integer variable tiε[0,1] to ith test vector such that ti = 1, if we select ti, otherwise ti= 0. • Define an integer constant fijε [0,1] such that fij = 1, if ith vector detects jth fault, otherwise fij = 0. Values of constants fij are determined by fault simulation. n minimize Σti Objective function i=1 n subject to Σfij ti ≥ N,j = 1, 2, . . ., m i=1 ELEC 7770: Advanced VLSI Design (Agrawal)

  30. N-Detect Tests (N = 5) ELEC 7770: Advanced VLSI Design (Agrawal)

  31. Why ILP Solution is Exponential? LP solution found in polynomial time (bound on ILP solution) Must try all 2n roundoff points Second variable Constraints First variable Objective (maximize) ELEC 7770: Advanced VLSI Design (Agrawal)

  32. Characteristics of ILP • Worst-case complexity is exponential in number of variables. • Linear programming (LP) relaxation, where integer variables are treated as real, gives a lower bound on the objective function. • Recursive rounding of relaxed LP solution to nearest integers gives an approximate solution to the ILP problem. • K. R. Kantipudi and V. D. Agrawal, “A Reduced Complexity Algorithm for Minimizing N-Detect Tests,” Proc. 20th International Conf. VLSI Design, January 2007, pp. 492-497. ELEC 7770: Advanced VLSI Design (Agrawal)

  33. Recursive Rounding Algorithm • Obtain a relaxed LP solution. Stopif each variable in the solution is an integer. • Round the variable closest to an integer. • Remove any constraints that are now unconditionally satisfied. • Go to step 1. ELEC 7770: Advanced VLSI Design (Agrawal)

  34. Complexity of Approximation • Recursive rounding: • ILP is transformed into k LPs with progressively reducing number of variables, where k is the size of the solution. • A solution that satisfies all constraints is guaranteed; this solution is often close to optimal. • Number of LPs, k, is the size of the final solution, i.e., the number of non-zero variables in the test minimization problem. • Recursive rounding complexity is k × O(np), where k ≤ n, n is number of variables. ELEC 7770: Advanced VLSI Design (Agrawal)

  35. Four-Bit ALU Circuit 14 inputs, 8 outputs ELEC 7770: Advanced VLSI Design (Agrawal)

  36. ILP vs. Recursive Rounding 100 75 50 25 0 ILP Recursive Rounding CPU s 0 5,000 10,000 15,000 Vectors ELEC 7770: Advanced VLSI Design (Agrawal)

  37. N-Detect Tests (N = 5) ELEC 7770: Advanced VLSI Design (Agrawal)

  38. A Primal-Dual Solution (N = 1) M. A. Shukoor and V. D. Agrawal, “A Primal-Dual Solution to Minimal Test Generation Problem,” Proc. 12th IEEE VLSI Design & Test Symp. (VDAT08), 2008, pp. 269-279. ELEC 7770: Advanced VLSI Design (Agrawal)

  39. Finding LP/ILP Solvers • R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling Language for Mathematical Programming, South San Francisco, California: Scientific Press, 1993. Several of programs described in this book are available to Auburn users. • B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K. R. Coombes, J. E. Osborn and G. J. Stuck, A Guide to MATLAB for Beginners and Experienced Users, Cambridge University Press, 2006. • Search the web. Many programs with small number of variables can be downloaded free. ELEC 7770: Advanced VLSI Design (Agrawal)

  40. A Circuit Optimization Problem • Given: • Circuit netlist • Cell library with multiple versions for each cell • Select cell versions to optimize a specified characteristic of the circuit. Typical characteristics are: • Area • Power • Delay ELEC 7770: Advanced VLSI Design (Agrawal)

  41. Example: Cell(X), X = 0 or 1 • X: an integer variable for each gate. • X = 0 • Delay = d • Power = 3 × p • X = 1 • Delay = 2 × d • Power = 0.5 × p • Cell delay = (1 – X) d + 2 X d • Power = 3(1 – X) p + 0.5 X p ELEC 7770: Advanced VLSI Design (Agrawal)

  42. ILP Model: Minimum Power & Delay Arrival time = T1 kth Cell Ti Arrival time = Tk Ti = signal arrival time at ith input; Ti = 0 for all PIs Tk = signal arrival time at cell output Tk≥ Ti + (1 – Xk) dk + 2 Xkdk, for all i Where, dk = nominal delay of gate Xk = 0 or 1, specifies version of cell Minimize α TPO + ∑ [3(1 – Xk) pk + 0.5 Xkpk] α is constant all k ELEC 7770: Advanced VLSI Design (Agrawal)

  43. Given Clock Specification Combinational Logic Register Register Clock Tj = 0, for all primary inputs j Tk≤ clock period, for all primary outputs k Tk≥ Ti + (1 – Xk) dk + 2 Xkdk, for all gates k with input i ELEC 7770: Advanced VLSI Design (Agrawal)

  44. Minimum Power Design Minimize ∑ 3(1 – Xk) pk + 0.5 Xkpk all k where pk = nominal power consumption of kth cell ELEC 7770: Advanced VLSI Design (Agrawal)

  45. Logic Minimization A D EPI’s C B Non-EPI’s Non-EPI’s Consider a four-variable function, {2,4,6,8,9,10,12,13,15} Karnaugh map shows prime implicants (PI) found by Quine-McCluskey procedure. Find the minimum number of Pis to cover all minterms. ELEC 7770: Advanced VLSI Design (Agrawal)

  46. Select a Minimal Set of PI’s • First select essential prime implicants (EPIs). • Cover remaining minterms with smallest number of prime implicants (Pis). ELEC 7770: Advanced VLSI Design (Agrawal)

  47. Cover Remaining Minterms Integer linear program (ILP): Define integer {0,1} variables, xk = 1, select PIk; xk = 0, do not select PIk. Minimize k xk, subject to following constraints: x2 + x3 ≥ 1 (cover minterm 2) x4 + x5 ≥ 1 (cover minterm 4) x2 + x4 ≥ 1 (cover minterm 6) x3 + x6 ≥ 1 (cover minterm 10) A solution is x3 = x4 = 1, x2 = x5 = x6 = 0 ELEC 7770: Advanced VLSI Design (Agrawal)

  48. Minimized Function A D EPI’s in MSOP C B Pis not selected Selected PIs F(A,B,C,D) = PI1 + PI3 + PI4 + PI7 = AC +B CD +A BD + A B D ELEC 7770: Advanced VLSI Design (Agrawal)

  49. Comb. Circuit Power Optimization • Given a set of test vectors • Reorder vectors to minimize the number of transitions at primary inputs Combinational circuit (tested by exhaustive vectors) 01010101 00110011 00001111 11 transitions 01111000 Rearranged vector set 00110011 produces 7 transitions 00011110 ELEC 7770: Advanced VLSI Design (Agrawal)

  50. Reducing Comb. Test Power Original tests: V1 V2 V3 V4 V5 1 3 4 V1 V2 V3 1 1 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 3 1 2 3 2 1 V4 V5 10 input transitions 2 Reordered tests: V1 V3 V5 V4 V2 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 Traveling salesperson problem (TSP) finds the shortest distance closed path (or cycle) to visit all nodes exactly once. But, we need an open loop solution. 5 input transitions ELEC 7770: Advanced VLSI Design (Agrawal)

More Related