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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2007 Control Unit: Hard-Wired and Microcoded (Chapter 5). Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal

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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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  1. ELEC 5200-001/6200-001Computer Architecture and DesignSpring 2007 Control Unit: Hard-Wiredand Microcoded (Chapter 5) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC 5200-001/6200-001 Lecture 9

  2. Alternatives for Control Unit (CU) • Hard-wired (hardware) • Random logic, programmable logic array (PLA), or ROM • Fast • Inflexible • Firmware • Microprogrammed or microcoded CU • Control implemented like a computer (microcomputer) • Microinstructions • Microprogramming • Flexible • Changes to instruction set possible • Completely different instruction sets can be emulated • Speed limited by microcomputer memory ELEC 5200-001/6200-001 Lecture 9

  3. Hardwired CU: Single-Cycle • Implemented by combinational logic. Control logic Datapath 6 funct. code Control signals To ALU 6 opcode 3 ALU control 2 ALUOp ELEC 5200-001/6200-001 Lecture 9

  4. Jump 0-25 Shift left2 0 mux 1 4 Add 1 mux 0 ALU Branch opcode MemtoReg CONTROL 26-31 RegWrite ALUSrc 21-25 zero MemWrite MemRead ALU Instr. mem. PC Reg. File Data mem. 1 mux 0 16-20 0 mux 1 1 mux 0 11-15 Single-cycle Datapath RegDst ALUOp ALU Cont. Sign ext. Shift left 2 0-15 0-5 ELEC 5200-001/6200-001 Lecture 9

  5. Single-Cycle Control Logic Op5 Op4 Op3 Op2 Op1 Op0 ALUOp1 MemtoReg MemRead ALUOp0 MemWrite RegWrite Jump Branch RegDst ALUSrc ELEC 5200-001/6200-001 Lecture 9

  6. Single-Cycle Control Circuit Op5 Op4 Op3 Op2 Op1 Op0 lw R sw beq J RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0 Jump ELEC 5200-001/6200-001 Lecture 9

  7. ALU Control Logic ELEC 5200-001/6200-001 Lecture 9

  8. ALU Control Operation select from control From Control Circuit ALUOp1 ALUOp0 3 zero ALU result F3 F2 F1 F0 overflow Operation select ALU function 000 AND 001 OR 010 Add 110 Subtract 111 Set on less than ELEC 5200-001/6200-001 Lecture 9

  9. Instr. decode/reg. fetch/branch addr. Instr. fetch/ adv. PC ALU operation Write PC on branch condition Write jump addr. to PC Compute memory addr. Write memory data Read memory data Write register Write register Hardwired Control Unit: Multicycle Inputs: 6 opcode bits Outputs: 16 control signals Start State 0 1 lw or sw J R B 3 2 lw 6 8 9 sw 4 5 7 ELEC 5200-001/6200-001 Lecture 9

  10. States and Outputs • 10 states can be encoded 0000 through 1001. • State code completely determines what 16 control signals are (Moore machine). • Next state ← present state + 1, with three exceptions: • State 1 (0001) – opcode must decide next state • State 2 (0010) for lw or sw • State 6 (0110) for R-type of instruction • State 8 (1000) for branch instruction • State 9 (1001) for jump instruction • State 2 (0010) – opcode must decide next state • State 3 (0011) for lw • State 5 (0101) for sw • States 4 (0100), 5 (0101), 7 (0111), 8 (1000) and 9 (1001) • Next state is 0 (0000) ELEC 5200-001/6200-001 Lecture 9

  11. Instr. decode/reg. fetch/branch addr. Instr. fetch/ adv. PC ALU operation Write PC on branch condition Write jump addr. to PC Compute memory addr. Write memory data Read memory data Write register Write register Hardwired Control Unit: Multicycle Inputs: 6 opcode bits Outputs: 16 control signals Start State 0000 0001 lw or sw J R 0011 B 0010 lw 0110 sw 1000 1001 0100 0101 0111 ELEC 5200-001/6200-001 Lecture 9

  12. Implementing with State Sequencer Control PLA or ROM 16 control signals PLA input or ROM address Select one of 4 ways Four flip-flops State sequencer 6-bit opcode ELEC 5200-001/6200-001 Lecture 9

  13. A ROM Implementation Control ROM Sixteen 18-bit words 4-bit address 16 Control signals to datapath 2 0001 AddrCtl go to 00 st. 0 11 st. + 1 01 st. 2,6,8,9 10 st. 3,5 Addr. 4 4-bit state flip-flops 4 MUX 11 10 01 00 Adder Adv. state 0000 4 Dispatch ROM 2 Dispatch ROM 1 Opcode from IR 6 ELEC 5200-001/6200-001 Lecture 9

  14. Dispatch ROM Contents Each dispatch ROM has sixty-four 4-bit words Address is 6-bit opcode Content is next state (4-bits) ELEC 5200-001/6200-001 Lecture 9

  15. Control ROM Contents • Control ROM has sixteen 18-bit words: • bits 0-1, AddrCtl to control mux • bits 2-17, sixteen control signals for datapath • Address is 4-bit state. ELEC 5200-001/6200-001 Lecture 9

  16. Microprogram: Basic Idea • The control unit in a computer generates an output (sequence of control signals) for each opcode; • Implement the control unit as a computer, within a computer, that executes a program for each opcode. • M. V. Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Report of Manchester University Computer Inaugural Conference, pp. 16-18, 1951. Reprinted in E. E. Swartzlander (editor), Computer Design Development: Principal Papers, pp. 266-270, Rochelle Park, NJ: Hayden, 1976. ELEC 5200-001/6200-001 Lecture 9

  17. Maurice V. Wilkes Born June 26, 1913, Staffordshire, UK 1967 Turing Award citation: Professor Wilkes Is best known as the builder and designer of the EDSAC, the first computer with an internally stored program. Built in 1949, the EDSAC used a mercury delay line memory. He is also known as the author, with Wheeler and Gill, of a volume on “Preparation of Programs for Electronic Digital Computers” in 1951, in which program libraries were effectively introduced. ELEC 5200-001/6200-001 Lecture 9

  18. Microcoded CU Microcode word Sixteen 18-bit words 4-bit address Microcode memory 16 Control signals to datapath 0001 AddrCtl Addr. Sequencing field 2 4 μPC 4-bit state flip-flops 4 MUX 11 10 01 00 Adder 0000 Dispatch ROM 2 Dispatch ROM 1 Opcode from IR Address select logic lw or sw sw, lw, R, B or J 6 ELEC 5200-001/6200-001 Lecture 9

  19. Implementing the Idea • Use a memory type implementation for control unit. • Create a software infrastructure to automatically translate instructions into memory data (microcode): • Microinstructions – define a machine language in which instructions can be described • Microprogram – an instruction described in microinstructions • Microassembler – converts microprogram to microcode • Is there a micro-compiler? ELEC 5200-001/6200-001 Lecture 9

  20. Microprogramming • A microinstruction set is defined. • To program the control of a computer for an instruction set, a programmer writes a microprogram for each machine instruction. • Each micrprogram is converted into microcode, specific to the datapath hardware, by a microassembler and the microcodes are loaded in the microcode memory of the CU. ELEC 5200-001/6200-001 Lecture 9

  21. Microinstruction Format • Label or name of microinstruction • Seven fields • ALU control add, subtract or funct. code # result to ALUOut • SRC1 PC or A • SRC2 B, 4, extend or extend-shift • Reg. control Read # read two reg. specified by IR into A & B Write ALU # write ALUOut to register file Write MDR # register file ← MDR • Memory Read PC # IR ← M[ PC ] Read ALU # MDR ← M[ ALUOut ] Write ALU # M[ ALUOut ] ← B • PCWrite ALU # write PC from ALU ALU cond. # If zero=1, PC ← ALUOut Jump addr. # PC ← jump address • Sequencing Seq # choose next μInst. Sequentially fetch # go to first μInst. to begin new instruction Dispatch i # use Dispatch ROM i, i = 1 or 2 ELEC 5200-001/6200-001 Lecture 9

  22. Instr. decode/reg. fetch/branch addr. Instr. fetch/ adv. PC ALU operation Write PC on branch condition Write jump addr. to PC Compute memory addr. Write memory data Read memory data Write register Write register Sequencing Decode1 Mem1 Fetch 1 Sequencing = seq State 0 Dispatch 1 LW2 JUMP1 SW2 BEQ1 3 2 R1 lw 6 Dispatch 2 8 seq 9 sw seq Fetch Fetch 4 5 7 Fetch Fetch Fetch ELEC 5200-001/6200-001 Lecture 9

  23. Microinstructions • Fetch • Decode • Mem1 • LW2 • SW2 • R1 • BEQ1 • JUMP1 ELEC 5200-001/6200-001 Lecture 9

  24. Microinstruction Fetch Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. Fetch Add PC 4 Read PC ALU Seq Microassembler produces the following microcode: 00 0 01 0 0 0 1 0 1 0 00 1 0 11 MemRead IorD IRWrite MemWrite RegWrite RegDst MemtoReg ALUOp PCSource PCWrite PCWriteCond Addrctl ALUSrcA ALUSrcB ELEC 5200-001/6200-001 Lecture 9

  25. Microinstruction Decode Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl ctrl ctrl Decode1 Add PC ExtShft Read Dispatch 1 Microassembler produces the following microcode: 00 0 11 0 0 0 0 0 0 0 00 0 0 01 MemRead IorD IRWrite MemWrite RegWrite RegDst MemtoReg ALUOp ALUSrcB PCSource PCWrite PCWriteCond ALUSrcA AddrCtl ELEC 5200-001/6200-001 Lecture 9

  26. μCode Generation ELEC 5200-001/6200-001 Lecture 9

  27. μCode Generation (Cont.) ELEC 5200-001/6200-001 Lecture 9

  28. μCode Generation (Cont.) ELEC 5200-001/6200-001 Lecture 9

  29. Microprogram for fetch Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. Fetch Add PC 4 Read PC ALU Seq Decode1 Add PC ExtShft Read Dispatch 1 Microassembler produces the following microcode: 00 0 01 0 0 0 1 0 1 0 00 1 0 11 00 0 11 0 0 0 0 0 0 0 00 0 0 01 MemRead IorD IRWrite MemWrite RegWrite RegDst MemtoReg PCSource PCWrite PCWriteCond ALUOp Addrctl ALUSrcA ALUSrcB ELEC 5200-001/6200-001 Lecture 9

  30. Microprogram for lw and sw Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. Mem1 Add A Extend Dispatch 2 LW2 Read ALU Seq Write MDR Fetch SW2 Write ALU Fetch Microprogram consists of four microinstructions. ELEC 5200-001/6200-001 Lecture 9

  31. Microprogram for R-Type Instruction Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. R1 Funct code A B Seq Write ALU Fetch Go to next μInstr. Go to μInstr. Fetch Microprogram consists of two microinstructions. ELEC 5200-001/6200-001 Lecture 9

  32. Microprogram for beq Instruction Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. BEQ1 Subt A B ALUOut-condFetch If (zero) then PC ← ALUOutGo to μInstr. Fetch Microprogram consists of one microinstruction. ELEC 5200-001/6200-001 Lecture 9

  33. Microprogram for jump Instruction Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. JUMP1 Jump addressFetch Microprogram consists of one microinstruction. ELEC 5200-001/6200-001 Lecture 9

  34. μProgram for Multi-Cycle CU Label ALU SRC1 SRC2 Reg. Mem. PCWrite Seq. ctrl. ctrl. ctrl. Fetch Add PC 4 Read PC ALU Seq Decode1 Add PC ExtShft Read Disp. Mem1 Add A Extend Disp. 2 LW2 Read ALU Seq Write MDR Fetch SW2 Write ALU Fetch R1 FntCd. A B Seq Write ALU Fetch BEQ1 Subt A B ALUOut-cond Fetch JUMP1 Jump address Fetch ELEC 5200-001/6200-001 Lecture 9

  35. Summary • Hard-wired control: A finite state machine implemented typically using programmable logic array (PLA) or random logic. • Microinstruction: A one-clock instruction that asserts a set of control signals to the datapath and specifies what microinstruction to execute next. • Microprogram: A sequence of microinstructions that implements a multicycle (or single cycle) instruction. • Microcode: Machine code of a microprogram, generally produced by a microassembler. • Microprogrammed or microcoded control: A method of specifying control that uses microcode rather than a finite state machine. ELEC 5200-001/6200-001 Lecture 9

  36. Further on Microprogramming • Terms “microcomputer” and “microarchitecture” are not related to microprogramming. • Nanoprogramming: Two levels of microprogramming – a “recursive” control: • Nanodata Corp., QM-1 Hardware Level Users Manual, 2nd Ed., Williamsville, NY, 1972. • J. P. Hayes, Computer Architecture and Organization, Section 4.4.3, NY: McGraw-Hill, 1978. • Virtual machines: Any program can be run on any instruction set using an interpreter. Example, Java. ELEC 5200-001/6200-001 Lecture 9

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