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Single Threaded CPU Profile S. Vishin MIPS Technologies

Single Threaded CPU Profile S. Vishin MIPS Technologies. Single Threaded CPU profile. Application: Cached or Non Cached CPU cores Single Threaded (Will add Tags later for OOO read requests) Features: Variable width(16, 24, 32, 64b), Address mapped Master Port

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Single Threaded CPU Profile S. Vishin MIPS Technologies

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  1. Single Threaded CPU ProfileS. VishinMIPS Technologies

  2. Single Threaded CPU profile • Application: • Cached or Non Cached CPU cores • Single Threaded (Will add Tags later for OOO read requests) • Features: • Variable width(16, 24, 32, 64b), Address mapped Master Port • Burst Model is SRMD with known, precise burst length. • Posted Write Model. • Cache Management commands and cache behavior mapped to MReqInfo. • Cache hierarchy mapped using MAddrSpace. • No use for RDLWRC/READEX. (Use interrupts/exceptions) • No use for MRespAccept.

  3. Features: Sideband Signals • Interrupt support skimpy. Could not map interrupts into OCP framework. Difficult problem as have 3 interrupt modes. At a minimum provide a vector of interrupt[..] in Slave sideband. • Serror used for errors on posted writes. • In general I found it difficult to map Sideband signals to Master Sideband or to Status Sideband ? Some mappings: • Sflags: Performance events, 2nd level Cache misses etc. • Mflags: Difficult to decide if signals map here or in Status? • Control: CPUID, Endianess, EJTAG info etc • Status: Powerdown states, BIST go/nogo. • Scan interface well defined, no such interface for BIST. • Scan control bit vector useful for adding ram Enable.

  4. Single Threaded CPU Profile MCmd, Maddr, Mdata, Mburst*, MByteEn, MReqInfo, MAddrSpace, MBurstLength Master Slave MCmd SCmdAccept Mdata, MDataByteEn MDataValid, MDataLast SDataAccept SData, SResp SRespLast MCmd ={ Idle | Write Post | Read } MBurstPrecise=1, MBurstSeq=XOR/WRAP, MburstSingleReq=1

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