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111 Single Cycle CPU

111 Single Cycle CPU. ENGR 3410 – Computer Architecture Mark L. Chang Fall 2006. Computer. Processor. Memory. Devices. Control. Input. Datapath. Output. Datapath & Control. Readings 5.1-5.4 Datapath: System for performing operations on data, plus memory access.

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111 Single Cycle CPU

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  1. 111Single Cycle CPU ENGR 3410 – Computer Architecture Mark L. Chang Fall 2006

  2. Computer Processor Memory Devices Control Input Datapath Output Datapath & Control • Readings 5.1-5.4 • Datapath: System for performing operations on data, plus memory access. • Control: Control the datapath in response to instructions.

  3. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP RS RT RD SHAMT FUNCT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP RS RT 16 bit Address/Immediate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP 26 bit Address Simple CPU Develop complete CPU for subset of instruction set Memory: lw, sw Branch: beq Arithmetic: addi Arithmetic: add, sub Jump: j Most other instructions similar

  4. Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Execution Cycle • Obtain instruction from program storage • Determine required actions and instruction size • Locate and obtain operand data • Compute result value or status • Deposit results in storage for later use • Determine successor instruction

  5. Processor Overview Overall Dataflow PC fetches instructions Instructions select operand registers, ALU immediate values ALU computes values Load/Store addresses computed in ALU Result goes to register file or Data memory

  6. Processor Design Convert instructions to Register Transfer Level (RTL) specification Instruction = Memory[PC]; PC = PC + 4; RTL specifies required interconnection of units Control designed to achieve given paths for each instruction

  7. Instruction Fetch Instruction = Mem[PC]; // Fetch Instruction PC = PC + 4; // Increment PC (32bit)

  8. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP RS RT RD SHAMT FUNCT Add/Subtract RTL Add instruction: add rd, rs, rt Instruction = Mem[PC]; Reg[rd] = Reg[rs] + Reg[rt]; PC = PC + 4; Subtract instruction: sub rd, rs, rt Instruction = Mem[PC]; Reg[rd] = Reg[rs] - Reg[rt]; PC = PC + 4;

  9. Instructions[31:0] Instruction Fetch Unit [25:21] [20:16] [15:11] Rs Rt Rd Aw Aa Ab Da Dw Db Register WrEn File Datapath for Reg/Reg Ops Reg[rd] = Reg[rs] op Reg[rt]; ALUcntrl RegWr

  10. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP RS RT 16 bit Address/Immediate Add Immediate RTL Add immediate instruction: addi rt, rs, imm Instruction = Mem[PC]; Reg[rt] = Reg[rs] + SignExtend(imm); PC = PC + 4;

  11. Instruction Fetch Unit Instructions[31:0] [15:0] [25:21] [20:16] [15:11] Rs Rt Rd Imm16 Aw Aa Ab Da Dw Db Register WrEn File SignExtnd Datapath + Immediate Ops Reg[rt] = Reg[rs] + SignExtend(imm); ALUcntrl RegWr

  12. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP RS RT 16 bit Address/Immediate Load RTL Load Instruction: lw rt, imm(rs) Instruction = Mem[PC]; Addr = Reg[rs] + SignExtend(imm); Reg[rt] = Mem[Addr]; PC = PC + 4;

  13. Instructions[31:0] Instruction Fetch Unit [15:0] [25:21] [20:16] [15:11] Rs Rt Rd Imm16 Aw Aa Ab Da Dw Db Register WrEn File SignExtnd WrEn Addr Din Dout Data Memory Datapath + Load Addr = Reg[rs] + SignExtend(imm); Reg[rt] = Mem[Addr]; Rd Rt RegDst Rt Rs ALUcntrl MemWr RegWr imm16 ALUSrc

  14. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP RS RT 16 bit Address/Immediate Store RTL Store Instruction: sw rt, imm(rs) Instruction = Mem[PC]; Addr = Reg[rs] + SignExtend(imm); Mem[Addr] = Reg[rt]; PC = PC + 4;

  15. Instructions[31:0] Instruction Fetch Unit [15:0] [25:21] [20:16] [15:11] Rs Rt Rd Imm16 Aw Aa Ab Da Dw Db Register WrEn File SignExtnd WrEn Addr Din Dout Data Memory Datapath + Store Addr = Reg[rs] + SignExtend(imm); Mem[Addr] = Reg[rt]; Note: State of RegWr, MemToReg? Rd Rt RegDst Rt Rs ALUcntrl MemToReg MemWr RegWr imm16 ALUSrc

  16. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP RS RT 16 bit Address/Immediate Branch RTL Branch Instruction: beq rs, rt, imm Instruction = Mem[PC]; Cond = (Reg[rs] – Reg[rt]) == 0; // Test equality if (Cond) PC = PC + 4 + SignExtend(imm)*4; // Neg for backward // *4: LSbits == 00 else PC = PC + 4;

  17. Instructions[31:0] Instruction Fetch Unit [15:0] [25:21] [20:16] [15:11] Rs Rt Rd Imm16 Aw Aa Ab Da Dw Db Register WrEn File SignExtnd WrEn Addr Din Dout Data Memory Datapath + Branch Cond = (Reg[rs] – Reg[rt]) == 0; if (Cond) PC = PC + 4 + SignExtend(imm)*4; else PC = PC + 4; Rd Rt RegDst Rt Rs ALUcntrl MemToReg MemWr RegWr imm16 ALUSrc

  18. Addr[31:2] Addr[1:0] Instruction Memory Adder SignExtnd PC Instruction Fetch + Branch Cond = (Reg[rs] – Reg[rt]) == 0; if (Cond) PC = PC + 4 + SignExtend(imm)*4; else PC = PC + 4; Cin Instr[31:0] imm16

  19. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 OP 26 bit Address Jump RTL Store Instruction: j target Instruction = Mem[PC]; PC = { PC[31:28], target[25:0], “00” };

  20. Concatenate Addr[31:2] Addr[1:0] Instruction Memory 0 1 Adder SignExtnd PC Instruction Fetch + Jump PC = { PC[31:28], target[25:0], “00” }; PC[31:28] “00” “1” Target Instr[25:0] Cin “0” Instr[31:0] imm16 Branch Zero

  21. Instruction Fetch Unit Aw Aa Ab Da Dw Db Register WrEn File SignExtnd WrEn Addr Din Dout Data Memory Complete Datapath Instructions[31:0] Branch Rd Rt Jump [15:0] [25:21] [15:11] [20:16] RegDst Rs Rt Rd Imm16 Rt Rs ALUcntrl MemToReg MemWr Zero RegWr imm16 ALUSrc

  22. Concatenate Addr[31:2] Addr[1:0] Instruction Memory PC[31:28] “00” “1” Target Instr[25:0] Cin Adder “0” Jump PC SignExtnd Instr[31:0] imm16 Branch Zero Complete Fetch Unit

  23. Control • Identify control points for pieces of datapath • Instruction Fetch Unit • ALU • Memories • Datapath muxes • Etc. • Use RTL for determine per-instruction control assignments

  24. Control Signals

  25. Instruction Fetch Unit 1 0 Aw Aa Ab Da Dw Db Register WrEn File 0 1 0 1 SignExtnd WrEn Addr Din Dout Data Memory Add Control add rd, rs, rtInstruction = Mem[PC];Reg[rd] = Reg[rs] + Reg[rt];PC = PC + 4; Instructions[31:0] Branch Rd Rt Jump [15:0] [25:21] [15:11] [20:16] RegDst Rs Rt Rd Imm16 Rt Rs ALUcntrl MemToReg MemWr Zero RegWr imm16 ALUSrc

  26. Instruction Fetch Unit 1 0 Aw Aa Ab Da Dw Db Register WrEn File 0 1 0 1 SignExtnd WrEn Addr Din Dout Data Memory Subtract Control sub rd, rs, rtInstruction = Mem[PC];Reg[rd] = Reg[rs] - Reg[rt];PC = PC + 4; Instructions[31:0] Branch Rd Rt Jump [15:0] [25:21] [15:11] [20:16] RegDst Rs Rt Rd Imm16 Rt Rs ALUcntrl MemToReg MemWr Zero RegWr imm16 ALUSrc

  27. Instruction Fetch Unit 1 0 Aw Aa Ab Da Dw Db Register WrEn File 0 1 0 1 SignExtnd WrEn Addr Din Dout Data Memory Load Control lw rt, imm(rs) Instruction = Mem[PC];Addr = Reg[rs] + SignExtend(imm);Reg[rt] = Mem[Addr];PC = PC + 4; Instructions[31:0] Branch Rd Rt Jump [15:0] [25:21] [15:11] [20:16] RegDst Rs Rt Rd Imm16 Rt Rs ALUcntrl MemToReg MemWr Zero RegWr imm16 ALUSrc

  28. Instruction Fetch Unit 1 0 Aw Aa Ab Da Dw Db Register WrEn File 0 1 0 1 SignExtnd WrEn Addr Din Dout Data Memory Store Control sw rt, imm(rs) Instruction = Mem[PC];Addr = Reg[rs] + SignExtend(imm);Mem[Addr] = Reg[rt]; Instructions[31:0] Branch Rd Rt Jump [15:0] [25:21] [15:11] [20:16] RegDst Rs Rt Rd Imm16 Rt Rs ALUcntrl MemToReg MemWr Zero RegWr imm16 ALUSrc

  29. Instruction Fetch Unit 1 0 Aw Aa Ab Da Dw Db Register WrEn File 0 1 0 1 SignExtnd WrEn Addr Din Dout Data Memory Branch Control beq rs, rt, immInstruction = Mem[PC];Cond = (Reg[rs] – Reg[rt]) == 0;if (Cond) PC = PC+4+SignExtend(imm)*4;else PC = PC + 4; Instructions[31:0] Branch Rd Rt Jump [15:0] [25:21] [15:11] [20:16] RegDst Rs Rt Rd Imm16 Rt Rs ALUcntrl MemToReg MemWr Zero RegWr imm16 ALUSrc

  30. Concatenate Addr[31:2] Addr[1:0] Instruction Memory 1 0 0 1 Adder SignExtnd PC Branch Control (cont.) beq rs, rt, immInstruction = Mem[PC];Cond = (Reg[rs] – Reg[rt]) == 0;if (Cond) PC = PC+4+SignExtend(imm)*4;else PC = PC + 4; PC[31:28] “00” “1” Target Instr[25:0] Cin “0” Jump Instr[31:0] imm16 Branch Zero

  31. Instruction Fetch Unit 1 0 Aw Aa Ab Da Dw Db Register WrEn File 0 1 0 1 SignExtnd WrEn Addr Din Dout Data Memory Jump Control j targetInstruction = Mem[PC];PC = { PC[31:28], target[25:0], “00” }; Instructions[31:0] Branch Rd Rt Jump [15:0] [25:21] [15:11] [20:16] RegDst Rs Rt Rd Imm16 Rt Rs ALUcntrl MemToReg MemWr Zero RegWr imm16 ALUSrc

  32. Concatenate Addr[31:2] Addr[1:0] Instruction Memory 1 0 0 1 Adder SignExtnd PC Jump Control (cont.) j targetInstruction = Mem[PC];PC = { PC[31:28], target[25:0], “00” }; PC[31:28] “00” “1” Target Instr[25:0] Cin “0” Jump Instr[31:0] imm16 Branch Zero

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