EELE 367 – Logic Design

1. EELE 367 – Logic Design • Module 5 – Sequential Logic Design with VHDL • Agenda • Flip-Flops & Latches • Counters • Finite State Machines • State Variable Encoding

2. Latches • Latches • we’ve learned all of the VHDL syntax necessary to describe sequential storage elements • Let’s review where sequential devices come from • SR Latch- To understand the SR Latch, we must remember the truth table for a NOR GateAB F 00 1 01 0 10 0 11 0

3. Latches • SR Latch- when S=0 & R=0, it puts this circuit into a Bi-stable feedback mode where the output is either:Q=0, Qn=1 Q=1, Qn=0AB FAB F 00 1 (U2) 00 1 (U1) 01 0 01 0 (U2) 10 0 (U1) 10 0 11 0 11 0 0 0 0 1 1 0 0 1 1 0 0 0

4. Latches • SR Latch- we can force a known state using S & R:Set (S=1, R=0)Reset (S=0, R=1) AB FAB F 00 1 (U1) 00 1 (U2) 01 0 01 0 (U1) 10 0 (U2) 10 0 11 0 (U2) 11 0 (U1) 0 1 1 0 0 1 1 0 0 1 1 0

5. Latches • SR Latch- we can write a Truth Table for an SR Latch as followsS R Q Qn . 0 0 Last Q Last Qn - Hold 0 1 0 1 - Reset 1 0 1 0 - Set 1 1 0 0 - Don’t Use- S=1 & R=1 forces a 0 on both outputs. However, when the latch comes out of this state it ismetastable. This means the final state is unknown.

6. Latches • S’R’ Latch- we can also use NAND gates to form an inverted SR LatchS’ R’ Q Qn . 0 0 1 1 - Don’t Use 0 1 1 0 - Set 1 0 0 1 - Reset 1 1 Last Q Last Qn - Hold

7. Latches • SR Latch w/ Enable- we then can add an enable line using NAND gates- remember the Truth Table for a NAND gateAB F 00 1 - a 0 on any input forces a 1 on the output 01 1 - when C=0, the two EN NAND Gate outputs are 1, which forces “Last Q/Qn” 10 1 - when C=1, S & R are passed through INVERTED 11 0

8. Latches • SR Latch w/ Enable- the truth table then becomesC S R Q Qn . 1 0 0 Last Q Last Qn - Hold 1 0 1 0 1 - Reset 1 1 0 1 0 - Set 1 1 1 1 1 - Don’t Use 0 x x Last Q Last Qn - Hold

9. Latches • D Latch- a modification to the SR Latch where R = S’ creates a D-latch- when C=1, Q <= D- when C=0, Q <= Last ValueC D Q Qn . 1 0 0 1 - track 1 1 1 0 - track 0 x Last Q Last Qn - Hold

10. Latches • VHDL of a D Latch architecture Dlatch_arch of Dlatch is begin LATCH : process (D,C) begin if (C=‘1’) then Q<=D; Qn<=not D; else Q<=Q; Qn<=Qn; end if; end process; end architecture;

11. Flip Flops • D-Flip-Flops- we can combine D-latches to get an edge triggered storage device (or flop) - the first D-latch is called the “Master”, the second D-latch the “Slave”MasterSlave CLK=0, Q<=D “Open” CLK=0, Q<=Q “Close” CLK=1, Q<=Q “Closed” CLK=1, Q<=D “Open” - on a rising edge of clock, D is “latched” and held on Q until the next rising edge

12. Flip Flops • VHDL of a D-Flip-Flop architecture DFF_arch of DFF is begin FLOP : process (CLK) begin if (CLK’event and CLK=1) then -- recognized by all synthesizers as DFF Q<=D; Qn<=not D; else Q<=Q; Qn<=Qn; end if; end process; end architecture;

13. Counters • Counters- special name of any clocked sequential circuit whose state diagram is a circle- there are many types of counters, each suited for particular applications

14. Counters • Binary Counter- state machine that produces a straight binary count- for n-flip-flops, 2n counts can be produced- the Next State Logic "F" is a combinational SOP/POS circuit- the speed will be limited by the Setup/Hold and Combinational Delay of "F"- this gives the maximum number of counts for n-flip flops

15. Counters • Toggle Flop- a D-Flip-Flop can product a "Divide-by-2" effect by feeding back Qn to D- this topology is also called a "Toggle Flop"

16. Counters • Ripple Counter- Cascaded Toggle Flops can be used to form rippled counter- there is no Next State Logic- this is slower than a straight binary counter due to waiting for the "ripple"- this is good for low power, low speed applications

17. Counters • Synchronous Counter with ENABLE- an enable can be included in a "Synchronous" binary counter using Toggle Flops- the enabled is implemented by AND'ing the Q output prior to the next toggle flop- this gives us the "ripple" effect, but also gives the ability to run synchronously- a little faster, but still less gates than a straight binary circuit

18. Counters • Shift Register- a chain of D-Flip-Flops that pass data to one another- this is good for "pipelining"- also good for Serial-to-Parallel conversion- for n-flip-flops, the data is present at the final state after n clocks

19. Counters • Ring Counter- feeding the output of a shift register back to the input creates a "ring counter"- also called a "One Hot"- The first flip-flop needs to reset to 1, while the others reset to 0- for n flip-flops, there will be n counts

20. Counters • Johnson Counter- feeding the inverted output of a shift register back to the input creates a "Johnson Counter"- this gives more states with the same reduced gate count- all flip-flops can reset to 0- for n flip-flops, there will be 2n counts

21. Counters • Linear Feedback Shift Register (LFSR) Counter- all of the counters based off of shift registers give far less states than the 2n counts that are possible- a LFSR counter is based off of the theory of finite fields- created by French Mathematician Evariste Galois (1811-1832)- for each size of shift register, a feedback equation is given which is the sum modulo 2 of a certain set of output bits- this equation produces the input to the shift register- this type of counter can produce 2n-1 counts, nearly the maximum possible

22. Counters • Linear Feedback Shift Register (LFSR) Counter- the feedback equations are listed in Table 8.26 of the textbook- It is defined that bits always shift from Xn-1 to X0 (or Q0 to Qn-1) as we defined the shift register previously- they each use XOR gates (sum modulo 2) of particular bits in the register chainex)nFeedback Equation 2 X2 = X1  X0 3 X3 = X1  X0 4 X4 = X1  X0 5 X5 = X2  X0 6 X6 = X1  X0 7 X7 = X3  X0 8 X8 = X4  X3  X2 X0 : : : :

23. Counters • Linear Feedback Shift Register (LFSR) Counterex) 4-flip-flop LFSR Counter Feedback Equation = X1  X0 (or Q2  Q3 as we defined it)# Q(0:3) Sin 0 1000 0 1 0100 0 2 0010 1 3 1001 1 4 1100 0 5 0110 1 6 1011 0 7 0101 1 8 1010 1 9 1101 1 10 1110 1 11 1111 0 12 0111 0 13 0011 0 14 0001 1 - this is 2n-1 unique counts repeat 1000

24. Counters • Counters in VHDL- strong type casting in VHDL can make modeling counters difficult (at first glance)- the reason for this is that the STANDARD and STD_LOGIC Packages do not define "+", "-", or inequality operators for BIT_VECTOR or STD_LOGIC_VECTOR types

25. Counters • Counters in VHDL- there are a couple ways that we get around this 1) Use the STD_LOGIC_UNSIGNED Package - this package defines "+" and "-" functions for STD_LOGIC_VECTOR - we can use +1 just like normal - the vector will wrap as suspected (1111 - 0000) - one catch is that we can't assign to a Port - we need to create an internal signal of STD_LOGIC_VECTOR for counting - we then assign to the Port at the end

26. Counters • Counters in VHDL using STD_LOGIC_UNSIGNEDuse IEEE.STD_LOGIC_UNSIGNED.ALL; -- call the package entity counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Direction : in STD_LOGIC; Count_Out : out STD_LOGIC_VECTOR (3 downto 0)); end counter;

27. Counters • Counters in VHDL using STD_LOGIC_UNSIGNED architecture counter_arch of counter is signal count_temp : std_logic_vector(3 downto 0); -- Notice internal signal begin process (Clock, Reset) begin if (Reset = '0') then count_temp <= "0000"; elsif (Clock='1' and Clock'event) then if (Direction='0') then count_temp <= count_temp + '1'; -- count_temp can be used on both LHS and RHS else count_temp <= count_temp - '1'; end if; end if; end process; Count_Out <= count_temp; -- assign to Port after the process end counter_arch;

28. Counters • Counters in VHDL 2) Use integers for the counter and then convert back to STD_LOGIC_VECTOR - STD_LOGIC_ARITH is a Package that defines a conversion function - the function is: conv_std_logic_vector (ARG, SIZE) - functions are defined for ARG = integer, unsigned, signed, STD_ULOGIC - SIZE is the number of bits in the vector to convert to, given as an integer - we need to keep track of the RANGE and Counter Overflow

29. Counters • Counters in VHDL using STD_LOGIC_ARITHuse IEEE.STD_LOGIC_ARITH.ALL; -- call the package entity counter is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Direction : in STD_LOGIC; Count_Out : out STD_LOGIC_VECTOR (3 downto 0)); end counter;

30. Counters • Counters in VHDL using STD_LOGIC_ARITH architecture counter_arch of counter is signal count_temp : integer range 0 to 15; -- Notice internal integer specified with Range begin process (Clock, Reset) begin if (Reset = '0') then count_temp <= 0; -- integer assignment doesn't requires quotes elsif (Clock='1' and Clock'event) then if (count_temp = 15) then count_temp <= 0; -- we manually check for overflow else count_temp <= count_temp + 1; end if; end if; end process; Count_Out <= conv_std_logic_vector (count_temp, 4); -- convert integer into a 4-bit STD_LOGIC_VECTOR end counter_arch;

31. Counters • Counters in VHDL 3) Use UNSIGNED data types #'s - STD_LOGIC_ARITH also defines "+", "-", and equality for UNSIGNED types - UNSIGNED is a Data type defined in STD_LOGIC_ARITH - UNSIGNED is an array of STD_LOGIC - An UNSIGNED type is the equivalent to a STD_LOGIC_VECTOR type - the equality operators assume it is unsigned (as opposed to 2's comp SIGNED) • Pro's and Cons- using integers allows a higher level of abstraction and more functionality can be included- easier to write unsynthesizable code or code that produces unwanted logic- both are synthesizable when written correctly

32. Counters • Ring Counters in VHDL- to mimic the shift register behavior, we need access to the signal value before and after clock'event- consider the following concurrent signal assignments: architecture …. begin Q0 <= Q3; Q1 <= Q0; Q2 <= Q1; Q3 <= Q2; end architecture…- since they are executed concurrently, it is equivalent to Q0=Q1=Q2=Q3, or a simple wire

33. Counters • Ring Counters in VHDL- since a process doesn't assign the signal values until it suspends, we can use this to model the "before and after" behavior of a clock event. process (Clock, Reset) begin if (Reset = '0') then Q0<='1'; Q1<='0'; Q2<='0'; Q3<='0';elsif (Clock'event and Clock='1') then Q0<=Q3; Q1<=Q0; Q2<=Q1; Q3<=Q2; end if; end process- notice that the signals DO NOT appear in the sensitivity list. If they did the process would continually execute and not be synthesized as a flip-flop structure

34. Counters • Johnson Counters in VHDL process (Clock, Reset) begin if (Reset = '0') then Q0<='0'; Q1<='0'; Q2<='0'; Q3<='0';elsif (Clock'event and Clock='1') then Q0<=not Q3; Q1<=Q0; Q2<=Q1; Q3<=Q2; end if; end process

35. Counters • Linear Feedback Shift Register Counters in VHDL process (Clock, Reset) begin if (Reset = '0') then Q0<='0'; Q1<='0'; Q2<='0'; Q3<='0';elsif (Clock'event and Clock='1') then Q0<=Q3 xor Q2; Q1<=Q0; Q2<=Q1; Q3<=Q2; end if; end process

36. Counters • Multiple Processes - we can now use State Machines to control the start/stop/load/reset of counters- each are independent processes that interact with each other through signals- a common task for a state machine is: 1) at a certain state, load and enable a counter 2) go to a state and wait until the counter reaches a certain value 3) when it reaches the certain value, disable the counter and continue to the next state- since the counter runs off of a clock, we know how long it will count between the start and stop

37. State Machines • State Machines- there is a basic structure for a Clocked, Synchronous State Machine 1) State Memory (i.e., flip-flops) 2) Next State Logic “G” (combinational logic) 3) Output Logic “F” (combinational logic) we’ll revisit F later…- if we keep this structure in mind while designing digital machines in VHDL, then it is a very straight forward task- Each of the parts of the State Machine are modeled with individual processes- let’s start by reviewing the design of a state machine using a manual method

38. State Machines • State Machines“Mealy Outputs” – outputs depend on the Current_State and the Inputs

39. State Machines • State Machines“Moore Outputs” – outputs depend on the Current_State only

40. State Machines • State Machines- the steps in a state machine design are: 1) Word Description of the Problem 2) State Diagram 3) State/Output Table 4) State Variable Assignment 5) Choose Flip-Flop type 6) Construct F 7) Construct G 8) Logic Diagram

41. State Machines • State Machine Example “Sequence Detector”1) Design a machine by hand that takes in a serial bit stream and looks for the pattern “1011”. When the pattern is found, a signal called “Found” is asserted2) State Diagram

42. State Machines • State Machine Example “Sequence Detector”3) State/Output TableCurrent_State In Next_State Out (Found) S0 0 S0 0 1 S1 0 S1 0 S2 0 1 S0 0 S2 0 S0 0 1 S3 0 S3 0 S0 0 1 S0 1

43. State Machines • State Machine Example “Sequence Detector”4) State Variable Assignment – let’s use binaryCurrent_State In Next_State Out Q1 Q0 Q1* Q0* Found 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 1 0 0 15) Choose Flip-Flop Type - 99% of the time we use D-Flip-Flops

44. State Machines • State Machine Example “Sequence Detector”6) Construct Next State Logic “F” Q1* = Q1’∙Q0∙In’ + Q1∙Q0’∙In Q0* = Q0’∙In Q1 Q1 Q0 In 00 01 11 10 0 0 2 1 6 0 4 0 0 0 1 0 3 7 0 1 5 1 In Q0 Q1 Q1 Q0 In 00 01 11 10 0 0 0 2 6 0 4 0 0 1 1 0 3 7 0 1 5 1 In Q0

45. State Machines • State Machine Example “Sequence Detector”7) Construct Output Logic “G” Found = Q1∙Q0∙In8) Logic Diagram - for large designs, this becomes impractical Q1 Q1 Q0 In 00 01 11 10 0 0 2 0 0 6 4 0 0 1 0 3 0 1 7 0 5 1 In Q0

46. State Machines in VHDL • State Memory- we use a process that updates the “Current_State” with the “Next_State”- we describe DFF’s using (CLK’event and CLK=‘1’)- this will make the assignment on the rising edge of CLK STATE_MEMORY : process (CLK) begin if (CLK’event and CLK='1') thenCurrent_State <= Next_State; end if; end process;- at this point, we need to discuss State Names

47. State Machines in VHDL • State Memory using “User-Enumerated Data Types"- we always want to use descriptive names for our states- we can use a user-enumerated type for this type State_Type is (S0, S1, S2, S3); signal Current_State : State_Type; signal Next_State : State_Type;- this makes our simulations very readable. • State Memory using “Pre-Defined Data Types"- we haven’t encoded the variables though, we can either leave it to the synthesizer or manually do it subtype State_Type is BIT_VECTOR (1 downto 0); constant S0 : State_Type := “00”; constant S1 : State_Type := “01”; constant S2 : State_Type := “10”; constant S3 : State_Type := “11”; signal Current_State : State_Type; signal Next_State : State_Type;

48. State Machines in VHDL • State Memory with “Synchronous RESET” STATE_MEMORY : process (CLK) begin if (CLK’event and CLK='1') then if (Reset = ‘1’) then Current_State <= S0; -- name of “reset” state to go to elseCurrent_State <= Next_State; end if; end if; end process;- this design will only observe RESET on the positive edge of clock (i.e., synchronous)

49. State Machines in VHDL • State Memory with “Asynchronous RESET” STATE_MEMORY : process (CLK, Reset) begin if (Reset = ‘1’) thenCurrent_State <= S0; -- name of “reset” state to go toelsif (CLK’event and CLK='1') thenCurrent_State <= Next_State; end if; end process;- this design is sensitive to both RESET and the positive edge of clock (i.e., asynchronous)

50. State Machines in VHDL • Next State Logic “F”- we use another process to construct “F”