MPS Software - Hardware

1. MPS Software - Hardware Coles Sibley 2000-0xxxx/vlb

2. MPS Software - Hardware • Application Software • IOC Software • MPS Hardware • Altera FPGA Code

3. MPS Software (A Separate review will be held for Software) • Database (Oracle generated files) • Run Permit System • Application software • SNL Programs • EPICS • MPS – PMC Driver Support (Stan Brown, LANL) • Device Support • Automated system checkout

4. ORACLE • EPICS database (From Template) • RPS configuration database • Alarms • Alarm actions • Access Security Files • Group, Machine, IP, etc. • IOC startup scripts • Archive files

5. MPS Software – Configuration files • Mode Mask Files • Global file, Contains ALL devices • MM Verification Files • IOC Specific, Mode verses MASK • IOC specific (MPS)Hardware Configuration Files • Version # • Software id • Serial # • Allowable jumpers • IOC Heartbeats

6. Run Permit System – Tasks • Machine Mode Setup • Machine Dump Selection • Beam Mode Selection (Power, Width restrictions) • Verifies machine setup before changing mode • Schedules Machine Sequence • Keeps Beam, RF, Modulator gates in sync • Schedules Pulse Profiles at requested rate • Calculates / verifies table checksums (pulse to pulse) • Operator Interface to MPS • Status / Trip Reset Displays • Mask / Trip limit Controls • Hardware configuration verification • SNL task scans IOC hardware configuration for verification

7. Machine Modes PPS /Beam Permit Ion Source D-Plate Linac Dump Injection Dump Ring Extraction Dump Target Beam Modes Off Standby (RFQ RF gate)? Diagnostics (10 usec) Diagnostics (50 usec) Diagnostics (100 usec) Full Pulse Width (1 msec) Low Power (7.5 kW) Medium Power (200 kW) Full Power (2 MW) Run Permit System – Mode Definitions

8. RPS – Operating Envelope Calculations

9. Pulse width – rep rate limitations • Pulse width indicated above is the integrated on time. Actual pulse width can increase according to the duty factor.

10. RTDL Data (24 bits + 8 bit CRC per frame) • 1 - Time of day 1 • 2 - Time of day 2 • 3 - Time of day 3 • Diagnostics and MPS will add fast counter times to time of day for time stamps • IOC’s will update clocks at 60 Hz • 4 - Event link period • (# psecs of ring revolution) • Used to convert counters to real time, ->IOCname:EventLinkPeriod.VAL • 5 - Operating mode • Defines beam dump in use and maximum beam power or maximum pulse length, whichever can deliver least beam power • MPS uses for Mode Masking • 6 - 60 Hz phase error • 60 hz zero crossing delta in psec, ->IOCname:LinePhaseError.VAL • Experimenters need value • LLRF for lookup table correction?

11. RTDL Data (cont) • 7 thru 14 - Pulse info • 8 frames can define a "standard" pulse (See next slide) • OR we could use the Pulse ID and EPICS waveform records • 15 - IOC Reset Address • Utility module uses for hard reset • 16 -Data Acquisition mode • Diagnostics • 17 - Pulse ID • Software input from Run Permit System • Defines one of 8 possible pulse profiles • IOC’s can use for Event triggered Record Processing • 18 thru 22 - Klystron_ok • 1 bit per klystron • Transmitter and modulator is logical OR of its klystron bits • 23 Kicker charge command • Beam will come in 16.6 msec (Not required if kickers are always charged) • 23 through 255 etc.

12. Beam Pulse, RR changes

13. HQA MPS Beam Off (Operator) Key Switch change Will turn off beam FPL FAULT Delay Mode change FPSL OK Run Permit Monitor MODE inputs Verify Equipment status Verify Power levels Verify pulse width limits Calculate Table checksums Swap RTDL Pointers MODE Changes

14. EPICS Driver Support (Initialization) • Initialization • Check configuration registers and initialize if required • Disable MPS Outputs • Enable MPS Mask register writes • Download Board specific mode masks • Verify Masks • Set default software masks • Disable mode mask writes • Enable MPS outputs

15. EPICS Driver Support (Interrupt) • Standard EPICS IO • Set / reset software masks • Set IOC heartbeat register as required • Enable / Disable MPS channels from Channel Access requests • Interrupts (60 Hz) Detection of RTDL Data Valid Event • Read and verify masks • Read and verify modes • Read cable connection status • Read jumper status

16. Interrupt routines, Device support – Cycle start • Interrupts (60 Hz) Detection of CYCLE_START Event • Read FPS counters • Read BPS counters • Read Fault counters • Read Status • “Touch” IOC heartbeat register • Inhibit beam if required for “Chatter Faults”, N trips in M seconds, etc. (Uses ENABLE / TEST input)

17. MPS Top Level Screen

18. Run Permit System – Operator Interface

19. Machine Protection System Hardware

20. SNS-MPS-VME module Input Signals • Eight (8) positive true, fail-safe fast protect latched inputs. • Eight (8) positive true, fail-safe fast protect auto reset inputs. • One 8 - MHz carrier input, FPAR link. • One 3 - MHz carrier input, FPL link. • One 16 - MHz carrier, bi-phase-mark modulated input event link. • One 10 - MHz carrier, bi-phase-mark modulated Real Time Data Link • One positive true, fail-safe PLC card bypass. • 16 – (8, FPSL,8,FPS) Software bypass enable jumpers

21. SNS-MPS-VME module Output Signals • One 8 - MHz carrier output, FPAR (Interlocked). • One 8 - MHz carrier output, FPAR (fan out). • One 3 - MHz carrier output, FPL (Interlocked). • One 3 - MHz carrier output, FPL (fan out) • Two – Positive LOW, FPAR (Open Collector) • Two – Positive LOW, FPAR Status

22. SNS-MPS-VME Chassis Indicators • One LED per MPS Input • MPS Input Channel Status • MPS Input Signal cable status • MPS Mode Mask • MPS Software Mask • Carrier Status (2 in, 2 out) • RTDL, Event Link Status (2) • MPS Mode in Use (5) • 3U chassis, 1U would be nice

23. MPS Interface Chassis front panel

24. MPS Interface Chassis PCB

25. MPS Grounding • Two ground planes, connectors tie to chassis, IC’s connected to VME ground • All inputs galvanically isolated • Outputs expected to be isolated • Shields, external grounds connect to Chassis ground, not directly to PCB ground • PCB ground connects to VME ground inside rack, Single point ground

26. MPS PMC Module (Also nice generic digital IO module)

27. PMC Module Screen dump (Success!) Here is a screens dump of the MPS board configuration test: -------------------------------------------------------------------------- snsELW> Starting program.....look for menu dialog on /tyCo/0 device BusNo = 0, DevNo = 10, FuncNo = 0 Config Word: 108310B5 Vendor ID/Device ID: 108310B5 Config Word: 8001 Config Word: 100000 Config Word: 200000 Config Word: 0 Config Word: 8101 Bus:Defice 00:00 Vendor/Device ID:00031057 Stat/Cmd: 20A00006 BAR0:00000008 Bus:Defice 00:0D Vendor/Device ID:000010E3 Stat/Cmd: 02000007 BAR0:00001000 BAR1:00800001 Bus:Defice 00:0E Vendor/Device ID:00191011 Stat/Cmd: 02800007 BAR0:00801001 BAR1:00002000 Bus:Defice 00:10 Vendor/Device ID:108310B5 Stat/Cmd: 02800003 BAR1:00008001 BAR2:00100000 BAR3:00200000 BAR5:00008101

28. PMC Test Screen dump --> Configuring Altera part using PPA mode and disk file data --> Number of conguration bytes written: 112151 --> Testing Interrupt assertion from Altera to 9050 --> Testing 256KB SRAM starting at 100000 --> First, test using data read/write of standard patterns --> Now performing address test - writing memory --> Now performing address test - reading memory --> SRAM test completed --> Now testing 'mirror' register --> Testing MAX902 circuit **> Error, XMDAT and XTCLK FF's are not high. Found: 0 --> Altera design revision: 1 --> Testing Altera Reset function --> Testing 100 ns delay lines --> PLL@0.75 MHz:PCIC: 2E97 PLLC: 10F Ratio: 0.99974847 . . . --> Now testing p[63..48] loopback to p[47..32] on rear panel Tests completed value = 0 = 0x0

29. Test Procedures • Functionality • Noise immunity • Crossed cables • HF noise rejection • Frequency checks • Signal cross talk measurements • Signal level immunity

30. MPS Hardware Status • Technobox PMC 96 channel reconfigurable IO module • Commercial item, several in house for testing • P2 Transition module (Passive) • Designed at LANL. Prototype in house for testing • MPS Input Chassis Display board • Designed at SNS. Prototype fabricated and tested • MPS Input Chassis, Interface PCB • Designed at SNS. Prototype fabricated and partially tested • WAGO IO block • Commercial item, several in house for testing • Fiber Optic transmitters, receivers • Brookhaven design, well tested, procurement in progress

32. MPS Altera Code Coles Sibley 2000-0xxxx/vlb

33. Altera Code Development • MAX Plus II version 10.0 • Hierarchical Design • Design Entry • AHDL code • Graphical input files • (RTDL code from utility module design)

34. Altera Logic Design

35. Version Control Date, version, ID, etc Status Registers Input, output, links, etc Mode Readback RTDL, Event Link, Combined (IN Use) Fault Counters Reset Registers Enable Registers Input channel enable, MASK write enable Mask Registers Mask RAM Heartbeat Registers One register per channel Different “WRITE_MASKS” for resets, enables, etc RAM writes are enabled, written to, locked PCI Bus Control (AHDL code)

36. MPS Mode MASK RAM (Graphical) • Uses internal 10K70 LPM_RAM • Enable writes • Download Mode Masks • Verify Mode Masks • Disable writes • Initializing RAM disables MPS carriers • Each RAM is 16 bits X 256 words • HI byte = MODE, Low byte = ~MODE • MODE Mask integrity verified pulse to pulse • MM_OK = MM[15..8] AND ~MM[7..0]

37. RTDL Receive Module (graphic and AHDL code) • XMITERR – Aborts Beam • CRC Error – Aborts Beam • Frequency checks • Data -> 24 bits • High Middle Low /(MODE) (MODE^2+1) (MODE) • Machine Mode, RTDL Frame # 5 • Inputs • 10 MHz RTDL data • Sys reset • Module outputs • Data Valid • Xmiterr • Parameter ID (Frame #) • Data (24 bits) • CRC Error • XDATCLK • Frequency check

38. Event Link Receiver (AHDL Code) • Similar to RTDL • Inputs • Event Link • PLL Clock • Delayed Data • Outputs • Event Valid • Event Strobe (One per Mode) • Xmitt error • Frequency check

39. Mode Compare (Graphical) • Verifies Event_Link_MODE == RTDL_MODE • 9 msec Heartbeat from Event link (Should get new mode and RTDL at 120 Hz) • Compares Time Of Day different from previous RTDL frame (No stale data) • Inputs • RTDL data • Event strobe • Time of Day • Outputs • Mode OK • MODE

40. MPS Input Circuit (Graphical) + Frequency verification Circuit on input carriers

41. MPS Output link logic (Graphical)

42. Fault Timer Circuits (Graphical) • Latches 16 MHz counter to record fault time • Latched on CYCLE_START Event, counter cleared at CYCLE_START +1 • Inputs • Input faults (from Input circuit) • RTDL, Event Link Errors • Fast Carrier Input fault detect • Outputs • Fault counter registers • (MSB indicates input is faulted or not)

43. Serial IN-OUT (Graphical) • Sends serial data for display • Parallel Inputs, Serial Outputs • SW Mask • Mode Mask • Channel Status • Link status • Serial Inputs, Parallel Outputs • Input cable status

44. MPS Heartbeat (Graphical) • Shuts off beam if IOC loses heartbeat (Reboot, crash, etc) • Inputs • Heartbeat Time • IOC HB signal • Reset • HB Jumper • Outputs • Keep alive • Status

45. FPGA Status • CODE approximately 75% complete • Basic functionality complete • 10K70 Resources are: • ** DEVICE SUMMARY ** • Chip/ Input Output Bidir Memory Memory LCs • POF Device Pins Pins Pins Bits % Utilized LCs % Utilized • mps_test EPF10K70RC240-3 45 41 38 6144 33 % 2082 55 % • User Pins: 45 41 38 • Next Step • Finish Event Link • Add timeouts, hardware error checks • Run Simulations