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VHDL for Combinational and Sequential Circuits

VHDL for Combinational and Sequential Circuits. MUX - using Selected Signal Assignment. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE mux2to1_arch OF mux2to1 IS BEGIN

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VHDL for Combinational and Sequential Circuits

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  1. VHDL for Combinational and Sequential Circuits

  2. MUX - using Selected Signal Assignment LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1,s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE mux2to1_arch OF mux2to1 IS BEGIN WITH s SELECT f <= w0 WHEN '0', w1 WHEN OTHERS ; END mux2to1_arch; Figure 6.27. VHDL code for a A 2-to-1 multiplexer.

  3. MUX - using Conditional Signal Assignment LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE mux2to1_arch OF mux2to1 IS BEGIN f <= w0 WHENs = '0' ELSE w1 ; END mux2to1_arch ; Figure 6.31. Specification of a 2-to-1 multiplexer using a conditional signal assignment.

  4. MUX - using if-then-else - Method 1 (Process specifies sensitivity list of all input signals) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE mux2to1_arch OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN IF s = '0' THEN f <= w0 ; ELSE f <= w1 ; END IF ; END PROCESS ; END mux2to1_arch ; Figure 6.38. A 2-to-1 multiplexer specified using an if-then-else statement

  5. MUX - using if-then-else - Method 2 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE mux2to1_arch OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN f <= w0 ; IF s = '1' THEN f <= w1 ; END IF ; END PROCESS ; END mux2to1_arch; Figure 6.39. Alternative code for a 2-to-1 multiplexer using an if-then-else statement.

  6. MUX - using CASE Statement LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END mux2to1 ; ARCHITECTURE mux2to1_arch OF mux2to1 IS BEGIN PROCESS ( w0, w1, s ) BEGIN CASEsIS WHEN '0' => f <= w0 ; WHEN OTHERS => f <= w1 ; END CASE ; END PROCESS ; END mux2to1_arch ; Figure 6.45. A case statement that represents a 2-to-1 multiplexer.

  7. 2-to-4 binary decoder - using PROCESS Statement LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END dec2to4 ; ARCHITECTURE dec2to4_arch OF dec2to4 IS BEGIN PROCESS ( w, En) BEGIN IF En = '1' THEN CASE w IS WHEN "00" => y <= "1000" ; WHEN "01" => y <= "0100" ; WHEN "10" => y <= "0010" ; WHEN OTHERS => y <= "0001" ; END CASE ; ELSE y <= "0000" ; END IF ; END PROCESS ; END dec2to4_arch ; Figure 6.46. A process statement that describes a 2-to-4 binary decoder.

  8. D flip-flop using Clock'EVENT AND Clock LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE flipflop_arch OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END flipflop_arch ; Figure 7.37. Code for a D flip-flop.

  9. D flip-flop with asynchronous reset ‘Resetn’ LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE flipflop_arch OF flipflop IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END flipflop_arch ; Figure 7.39. D flip-flop with asynchronous reset.

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