HDL for Combinational Circuits

1. HDL for Combinational Circuits ENEL211 Digital Technology

2. Lecture Outline • Vectors • Modular design • Tri-state gates • Dataflow modelling • Behavioural Modelling

3. Vectors • Often we want multi-bit quantities in digital circuits – bytes, samples, codes, etc. • Instead of specifying one wire for each bit we can specify the complete quantity as a vector • e.g. output [0:3]D; wire [7:0]SUM;

4. Vectors • The MSB of the vector is first, LSB last. • Can address individual bits of a vector e.g. D[2] • Can address parts of a vector e.g. SUM[5:3];

5. 2 to 4 line Decoder

6. 2 to 4 line Decoder Example module decoder_gl (A,B,E,D); input A,B,E; output [0:3]D; wire Anot,Bnot; not n1 (Anot,A), n2 (Bnot,B), and n4 (D[0],Anot,Bnot,E), n5 (D[1],Anot,B,E), n6 (D[2],A,Bnot,E), n7 (D[3],A,B,E); endmodule

7. Modular Design • Once a module has been designed it can be used by other modules. • This way a design hierarchy can be built up. • Module definitions cannot be placed inside another module, they must be defined externally and then incorporated through instantiation.

8. 4 bit Adder

9. Half Adder module halfadder (S,C,x,y); input x,y; output S,C; //Instantiate primitive gates xor (S,x,y); and (C,x,y); endmodule

10. Full Adder module fulladder (S,C,x,y,z); input x,y,z; output S,C; wire S1,D1,D2; //Outputs of first XOR and two AND gates //Instantiate the halfadder halfadder HA1 (S1,D1,x,y), HA2 (S,D2,S1,z); or g1(C,D2,D1); endmodule

11. 4 bit Adder module _4bit_adder (S,C4,A,B,C0); input [3:0] A,B; input C0; output [3:0] S; output C4; wire C1,C2,C3; //Intermediate carries //Instantiate the fulladder fulladder FA0 (S[0],C1,A[0],B[0],C0), FA1 (S[1],C2,A[1],B[1],C1), FA2 (S[2],C3,A[2],B[2],C2), FA3 (S[3],C4,A[3],B[3],C3); endmodule

12. Tri-state gates • Binary gates have two states: 0 or 1. • Sometimes it is useful to have a third state: “undefined” • In practice undefined is a high-impedance (or open circuit) state where the output has no effect on connected circuits. • This is useful for allowing multiple outputs to be connected together (e.g. to a bus)

13. Tri-state Buffers

14. Multiplexor • Multiplexor is a combinational circuit where an input is chosen by a select signal. • Two input mux • output =A if select =1 • output= B if select =0 A x B s

15. Two Input Multiplexor • A two-input mux is actually a three input device. A x B s x = A.s + B.s

16. Tri-state 2-Input Mux

17. Tri-state 4-Input Mux

18. Tri-state Gates in HDL • High-impedance state is z • Non-inverting gate is bufif1(output, input, control) bufif1(Y, A, C) if C=1, Y=A else Y=z

19. Tri-state Gates bufif1(Y,A,C) notif1(Y,A,C) notif0(Y,A,C) bufif0(Y,A,C)

20. 2-Input Tri-state Mux module muxtri (A,B,select,OUT); input A,B,select; output OUT; //use tri data type for output tri OUT; bufif1 (OUT,A,select); bufif0 (OUT,B,select); endmodule

21. Dataflow modelling • Another level of abstraction is to model dataflow. • In dataflow models, signals are continuously assigned values using the assign keyword. • assign can be used with Boolean expressions. • Verilog uses & (and), | (or), ^ (xor) and ~ (not) • Logic expressions and binary arithmetic are also possible.

22. Dataflow description of 2 to 4 line Decoder module decoder_df (A,B,E,D); input A,B,E; output [0:3] D; assign D[0] = ~A & ~B & E, D[1] = ~A & B & E, D[2] = A & ~B & E, D[3] = A & B & E; endmodule

23. Dataflow description of 4 bit Adder module binary_adder (A,B,Cin,SUM,Cout); input [3:0] A,B; input Cin; output [3:0] SUM; output Cout; assign {Cout,SUM} = A + B + Cin; endmodule

24. Dataflow description of 2-input Mux • Conditional operator ?:takes three operands: condition? true_expression : false_expression module mux2x1_df (A,B,select,OUT); input A,B,select; output OUT; assign OUT = select ? A : B; endmodule

25. Behavioural Modelling • Represents circuits at functional and algorithmic level. • Use proceedural statements similar in concept to proceedural programming languages (e.g. C, Java), • Behavioural modelling is mostly used to represent sequential circuits.

26. Behavioural Modelling • Behavioural models place proceedural statements in a block after the always keyword. • The always keyword takes a list of variables. The block of statements is executed whenever one of the variables changes. • The target variables are of type reg. This type retains its value until a new value is assigned.

27. Behavioral description of 2-input mux module mux2x1_bh(A,B,select,OUT); input A,B,select; output OUT; reg OUT; always @ (select or A or B) if (select == 1) OUT = A; else OUT = B; endmodule

28. Behavioral description of 4-input mux module mux4x1_bh (i0,i1,i2,i3,select,y); input i0,i1,i2,i3; input [1:0] select; output y; reg y; always @ (i0 or i1 or i2 or i3 or select) case (select) 2'b00: y = i0; 2'b01: y = i1; 2'b10: y = i2; 2'b11: y = i3; endcase endmodule

29. HDL Summary • Hardware Description Languages allow fast design and verification of digital circuits. • Accurate simulation and testing requires delays and inputs to be specified. • There are three different levels of abstraction for modelling circuits. • Primative (gate level) • Dataflow • Behavioral