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Nikola Markovic

Simulator for Hardware acceleration of STM www.bscmsrc.eu. Nikola Markovic. Motivation for building Simulator: X86 architecture (Intel, AMD) will become more pervasive in the many-core future Alltough many X86 simulators exist (M5, PTLSIM), no multi-core support exists

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Nikola Markovic

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  1. Simulator for Hardware acceleration of STM www.bscmsrc.eu Nikola Markovic • Motivation for building Simulator: • X86 architecture (Intel, AMD) will become more pervasive in the many-core future • Alltough many X86 simulators exist (M5, PTLSIM), no multi-core support exists • Goal: Extend M5 simulator to simulate multithreaded benchmarks for x86 architecture M5 Simulator: • Encompasses system-level architecture as well as processor microarchitecture • Implemented in Python and C++ • Distinguishing feature – Object Oriented Tool • Currently it provides three interchangeable CPU objects • A simple, functional, single CPI CPU • A detailed model of an out-of-order SMT capable CPU • A random memory-system tester • Specifically suited for cache architecture simulation What is done and current work: • We are adding support for executing multithreaded simulations for x86 architecture in M5 Simulator • Added several system calls to M5 simulator • Rt_sigprocmask • Rt_sigaction • Added functions that copy data from user space to simulator space and vice versa • Added two new microops, that were necessary for the proper implementation of xchg instruction, to x86 model in M5 simulator • Ldstl (load store locked) • Stl (store locked) • Implemented bus locking for x86 model of CPU in M5 by acquiring a bus token • Created simplified pthread library Future work: • Extend M5 Simulator to run all STAMP benchmarks – until now Labyrinth and Vacation benchmarks work • Extend M5 Simulator to run GHC (Glasgow Haskell Compiler) generated code • Explore hardware/software ideas in M5 simulator for speeding up TM in GHC M5 Simulator execution model Layer for TM extension

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