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CS 140 Lecture 17 System Designs III

CS 140 Lecture 17 System Designs III. Professor CK Cheng CSE Dept. UC San Diego. System Designs. Methodology Hierarchy Flow and Process Technology-Oriented Construction. Digital Designs vs Computer Architectures. Instruction Set (Chapter 6, CSE141) Bottleneck: Silicon Area, Power

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CS 140 Lecture 17 System Designs III

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  1. CS 140 Lecture 17System Designs III Professor CK Cheng CSE Dept. UC San Diego

  2. System Designs • Methodology • Hierarchy • Flow and Process • Technology-Oriented Construction

  3. Digital Designs vs Computer Architectures • Instruction Set (Chapter 6, CSE141) • Bottleneck: Silicon Area, Power • Data Path (Chapter 7) • Control Subsystem (Chapter 7) • Memory Management (Chapter 8, CSE141) • Bottleneck: IO, Memory Latency

  4. Design Process • Program of Hardware Description • List of Data Operations • Data Path • Read control signals. Output conditions • Control Subsystem • Read conditions. Output control signals

  5. Example: Multiplication • Input X, Y • Output Z • Variable M, i • M<=0 • For i=0 to N-1 • If Y0=1, M<=M+X • Shift Y right by one bit • Shift X left by one bit • Z<=M Z=X x Y • M<=0 • For i=0 to N-1 • If Yi=1, M<=M+X 2i • Z<=M

  6. Implementation: Example { Input X<15:0>, Y<15:0> type bit-vector, start type boolean; Local-Object A<31:0>, B<15:0> ,M<31:0>, i<4:0> type bit-vector; Output Z<31:0> type bit-vector, done type boolean; S0: If start’ goto S0; S1: A <= X || B <= Y || i<=0 || M<=0 || done <= 0; S2: If B0 = 0 goto S4 || i<=i+1; S3: M <= M+A || A<=Shift(A,L,1) || B<=Shift(B,R,1); S4: If i<16, goto S2; S5: Z<= M|| done<= 1|| goto S0; }

  7. Implementation: Example { Input X<15:0>, Y<15:0> type bit-vector, start type boolean; Local-Object A<31:0>, B<15:0> ,M<31:0>, i<4:0> type bit-vector; Output Z<31:0> type bit-vector, done type boolean; S0: If start’ goto S0; S1: A <= X || B <= Y || i<=0 || M<=0 || done <= 0; S2: If B0 = 0 goto S4 || i<=i+1; S3: M <= M+A || A<=Shift(A,L,1) || B<=Shift(B,R,1); S4: If i<16, goto S2; S5: Z<= M|| done<= 1|| goto S0; }

  8. Z=XY 16 32 X Data Subsystem Z 16 Y B0 i4 C0-7 Control Subsystem done start

  9. Data Path Subsystem operation A  Load (X) B  Load (Y) M Clear(M) i Clear(i) i  INC(i) M Add(M,A) A  SHL(A) B  SHR(B) Wires control C0 C2 C4 C6 C7 C5 C1 C3 A <= X B <=Y M<=0 i<=0 i<=i+ 1 M<=M+A A<=Shift(A,L,1) B<=Shift(B,R,1) Z<=M

  10. Data Path Subsystem 16 A Add 0 X M 16 LD SHL Z CLR LD C0 C1 C4 C5 i B i<4> Y CLR Inc LD SHR B<0> Control Unit C6 C7 i<4> C2 C3 C0-7 B<0> done start

  11. Control Subsystem A Add X M LD SHL Z CLR LD C0 C1 C4 C5 i B i<4> Y CLR Inc LD SHR B<0> C6 C7 C2 C3

  12. Control Subsystem S0 start’ start S1 S5 i<4>’ S2 i<4> B<0>’ B<0> S3 S4

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