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Micromachining for Integrated Electronics

Explore micromachined capacitors for enhanced performance in RF circuits, overcoming limitations such as pull-in effects, with a focus on design, fabrication, and testing techniques for wide tuning ranges.

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Micromachining for Integrated Electronics

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  1. Micromachining for Integrated Electronics Chang Liu Micro Actuators, Sensors, Systems Group University of Illinois at Urbana-Champaign Power and Energy Systems Seminar, ECE 490 I 9/24/2001 MASS UIUC

  2. Outline • Overview - MEMS for circuit applications • Micromachined tunable capacitors • Micromachined high-Q inductors • Conclusions MASS UIUC

  3. MEMS Applications MASS UIUC

  4. A Future Wireless World …Small, Low Power and Low Cost Collision avoidance radar Wireless LAN MASS UIUC

  5. Ultimate Miniaturization GPS Cellular Phone 30 GB memory True color display DC-200KHZ microphone Pressure sensor Pulse sensors Heart monitor Personal digital assistance Digital camera and movie Large screen projection display MASS UIUC

  6. MEMS for Integrated Electronics • RF Circuits • high performance, integrated components including • capacitors, • inductors, • resonators, • filters, • switches. • High performance integrated probes for circuit characterization • ability to interrogate sub-micrometer structures • Power electronics and energy systems • Capacitors • Inductors • Relays and switches • Transformers MASS UIUC

  7. MASS UIUC

  8. Integrated Power Generation and Conversion Portable generation and conversion for High power density High voltage applications MASS UIUC

  9. s BioMicrofluidics Applications for Integrated Lab-on-a-Chip MASS UIUC

  10. Outline • Overview - MEMS for circuit applications • Micromachined tunable capacitors • Micromachined high-Q inductors • Conclusions Moore’s law for integrated circuits MASS UIUC

  11. Background & Motivation • Current tunable capacitors • Performance limiting “pull-in” effect in micromachined parallel-plate tunable capacitors • Design, Fabrication and Testing • Design How to overcome the “pull-in” effect and achieve a wide tuning range? • Fabrication How to make it ? • Testing and measurement • Conclusions MASS UIUC

  12. Existing Tunable Capacitor Overview • Solid-state Varactors • High substrate resistive loss • Limited tuning range (<10%) • MEMS tunable capacitors • Lower loss • Wider tuning range • Typical example – electrostatically actuated parallel-plate tunable capacitor Diode MOS Capacitor Suspended plate VDC C Fixed plate MASS UIUC

  13. Pull-in Effect in Electrostatically ActuatedParallel-Plate Tunable Capacitors Pull-in effect is an intrinsic phenomenon to electrostatically actuated devices, which greatly limits the tuning range of the tunable capacitor. MASS UIUC

  14. Pull-in Effect in Electrostatically ActuatedParallel-Plate Tunable Capacitors Suspended plate x0 C Fixed plate Spacing Capacitance x0 0 0 VDC VDC MASS UIUC

  15. Pull-in Effect in Electrostatically ActuatedParallel-Plate Tunable Capacitors Suspended plate VDC C Fixed plate Spacing Capacitance x0 0 0 VDC VDC MASS UIUC

  16. Pull-in Effect in Electrostatically ActuatedParallel-Plate Tunable Capacitors Suspended plate VPI Fixed plate Controllable displacement Spacing Capacitance Unstable Snap-in x0 VPI 0 0 VDC VPI VDC Max. controllable tuning range = 50% MASS UIUC

  17. To Extend Tuning Range … • Require full-gap positioning Capacitance Spacing x0 0 0 VDC VPI VPI MASS UIUC

  18. Design of the Novel Tunable Capacitor Conventional design New design Suspended plate Suspended plate x d2 VDC=0V VDC d1 C C Fixed plate Fixed plates Suspended plate x0/3 Suspended plate VPI 2d2/3 VPI C Fixed plates Fixed plate d1 -d2/3 Max. C/C0 = 50% Max. C/C0 = 100% MASS UIUC US Patent Pending

  19. Fabrication Process (d) (a) (e) (b) (f) (c) MASS UIUC

  20. SEM Micrograph of the Tunable Capacitor E1 Etch hole MASS UIUC

  21. Simulation/Optimization • Electromechanically coupled simulation (MEMCAD*) • Base capacitance (C0) • Pull-in voltage (VPI) • Maximum Tuning range (C/C0) • Dynamic characteristic of the movable plate suspension • High frequency performance (Sonnet em Suite*) • Loss • Capacitive behavior * MEMCAD - Microcosm Inc, MA * Sonnet em Suit - Sonnet Software, Inc, NY MASS UIUC

  22. MEMCAD Model for C-V Simulation Suspended plate x Fixed plates Travel distance (x) of the top plate (E1) when a DC driving voltage (VDC) is applied between E1 andE3 MEMCAD model showing 3 plates of the wide tuning range tunable capacitor (See from the bottom) MASS UIUC

  23. Measured Simulated 45MHz • Return loss < 0.6dB@10GHz • Linear phase-frequency relationship 10GHz MASS UIUC

  24. Experiment Pull-in VDC=0V • d1 decreases continuously from 2 m to 1.2 m. Then d1 decreases abruptly from 1.2 m to 0.6m at VDC=17.2V. • The top plate travels 0.8 m (>d1/ 3) before the Pull-in occurs. VDC=16V MASS UIUC

  25. Results achieved • A new design concept for parallel-plate tunable capacitor to achieve arbitrary tuning range • A maximum tuning range of 70% achieved experimentally • Low loss (<0.6dB@10GHz) and excellent capacitive behavior at high frequencies MASS UIUC

  26. Outline • Overview - MEMS for circuit applications • Micromachined tunable capacitors • Micromachined high-Q inductors • Conclusions MASS UIUC

  27. 2nd Metal layer 1st Metal layer SiO2 Si Conventional Spiral Inductors • Occupy relatively large substrate space (~100100m2) • Suffer loss and parasitics from lossy substrate • Limited quality factor (Q) • Limited self-resonant frequency MASS UIUC

  28. Limitations of Current Micromachined Planar Coil Inductors Si Si Si Completely removing substrate material underneath (Ozgur) Partially removing substrate material underneath (Yeh) Air Gap Polyimide Si Glass Applying a thick polyimide layer underneath (Kim) Levitating the inductor structure above the substrate (Park, Yoon) • Still requiring relatively large substrate real estate (~100100m2) • Involving complex microfabrication steps, possibly incompatible with IC fabrication foundry MASS UIUC

  29. Fabrication Process of Vertical Spiral Inductors • Fabrication begun with a IC chip • Deposition of Permalloy • Sacrificial layer etching • Deposition of sacrificial layer • Fabrication of spiral inductor • Inductor assembly using PDMA MASS UIUC

  30. Assembly Using Micro Hinged Structures Main flap Secondary flap Cantilever beam spring loading mechanism • Require additional substrate estate for supporting structures or actuators • Difficult to create electrical path between the 3D structures and the substrate • Major application: Optical MEMS Electrical connection to substrate **-Yong Yi and C. Liu, IEEE J. Microelectromechanic. Syst. vol. 8, no. 1, pp .10-17, 1999. MASS UIUC

  31. Assembly Using Phase Changing Materials Phase changing material Micro flap Heat • Phase changing material: solder or photo resist • Requires heating to melt bulky phase changing material • Requires delicate control to attain uniform assembly **- R. R. A. Syms, IEEE J. Microelectromechanic. Syst. vol. 4, no. 4, pp. 177-184, 1995. **-K. F. harsh, V. M. Bright, and Y. C. Lee, Sensors & Actuators A., vol. 77, pp. 237-244, 1999. MASS UIUC

  32. Motivation of This Work • To develop an alternative general-purpose 3D assembly process • High density, uniform and efficient assembly • Solid electrical path between the 3D structure and the substrate • Room temperature assembly • Compatible with IC Foundry MASS UIUC

  33. Plastic Magnetic Deformation Assembly (a1) Surface-micromachining of the structure to be assembled (a2) Deposition of the magnetic material piece (b) Application of an external magnetic field (strength & direction) to create required plastic deformation in the flexible region Magnetic material can be removed afterwards if necessary. MASS UIUC

  34. Plastic Magnetic Deformation Assembly After PDMA Before PDMA • Supporting structure not required  High density • Magnetic actuation  Room temperature process • 3D structures aligned to the external magnetic filed  Uniformity • Metal used as bending material  Solid electrical path • IC compatible MASS UIUC

  35. Plastic Magnetic Deformation Assembly • Structures may fall back to a certain angle () after Hext is removed due to the elastic energy stored in microstructure during the bending. MASS UIUC

  36. Theoretical Analysis For a specific PDMA implementation, we need to know the relationship between Hext and the bending angle () beforehand, so that the targeted final rest angle () can be achieved. MASS UIUC

  37. Theoretical Analysis Magnetic Force: Tm = MwptplpHextcos=MVpHextcos The magnetic force tries to align the cantilever beam to the magnetic field M - Magnetization of Permalloy wp, tp and lp – width, thickness and length of Permalloy MASS UIUC

  38. Theoretical Analysis When Hext is increased, the bending experiences two phases. Phase 1: Elastic bending (at small s) Eg – Young’s Modulus of gold M – Magnetization of the Permalloy piece y– Yield stress of gold Ig – Moment of inertia of the gold beam lg – Length of the gold beam wg – Width of the gold beam tg – Thickness of the gold beam lp – Length of the Permalloy wp – Width of the Permalloy tp – Thickness of the Permalloy Vp – volume of the Permalloy piece Phase 2: Plastic bending (at large s) MASS UIUC

  39. Theoretical Analysis When Hext is increased, the bending experiences two phases. Phase 1: Elastic bending Plastic Bending angle () Phase 2: Plastic bending Elastic Hext MASS UIUC

  40. Theoretical Analysis  Plastic Bending angle () Yielding Elastic Hext • The bending is first elastic and then plastic. • The bending angle () saturates when Hext increases since the magnetic force tries to align the cantilever beam to the magnetic field. • The final rest angle () is determined by the bending angle occurring in the plastic regime. MASS UIUC

  41. Measured Displacement Vs. Hext Bending angle () Hext(Amps/m) MASS UIUC

  42. Experimental Results   Larger lg Smaller lg Rest angle () lg(m) MASS UIUC

  43. Other Issues Creating vertical structure Post-assembly Strengthening 3 m Parylene coating MASS UIUC

  44. Scanning Electron Micrographs of Fabricated Prototype Devices Before PDMA After PDMA MASS UIUC

  45. Experimental Results Inductoron Silicon Vertical inductor Inductor on Glass • Inductance = 4.5nH • Max Q inductor on Silicon = 3.5 • Max Q vertical inductor = 12 • Max Q inductor on glass = 12 MASS UIUC

  46. 3D Solenoid MASS UIUC

  47. 3D Solenoid MASS UIUC

  48. Outline • Overview - MEMS for circuit applications • Micromachined tunable capacitors • Micromachined high-Q inductors • Conclusions MASS UIUC

  49. Conclusions • Potentials for applying micromachining technology to circuit and power electronics applications • Developed variable gap tunable capacitor architecture and demonstrated large tuning range; • Developed three-dimensional assembly technique and realized high qualify factor inductor elements; • Current and future work: • Develop integrated power convertors for on-chip power regulation. • Develop tunable, lockable and resettable micro capacitors. • Develop high-Q inductors and demonstrate integration onto IC chips. MASS UIUC

  50. Acknowledgements • This research is supported by the Grainger Center and DARPA. • Thanks for discussions from Professor Krein and Professor Chapman. MASS UIUC

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