Computer Systems

1. Computer Systems Virtual Memory Computer Systems – virtual memory

2. 0: 1: CPU N-1: A System with Virtual Memory Memory Page Table Virtual Addresses Physical Addresses 0: 1: P-1: Disk • Address Translation: Hardware converts virtual addresses to physical addresses via lookup table (page table) Computer Systems – virtual memory

3. Object Name X Data 0: 243 D: 1: 17 J: • • • N-1: 105 X: VM advance #1: Caching Tool • DRAM Cache (Main Memory) • Each allocated page of virtual memory has entry in page table • Mapping from virtual pages to physical pages • From uncached form to cached form • Page table entry even if page not in memory • Specifies disk address Page Table “Cache” Location 0 On Disk • • • 1 Computer Systems – virtual memory

4. “Cache” Tag Data 0: Object Name J D X 105 17 243 = X? 1: X • • • • • • N-1: Locating an Object in a “Cache” • SRAM Cache (level 1 en level 2) • Tag stored with cache line • Maps from cache block to memory blocks • From cached to uncached form • Save a few bits by only storing tag • No tags for blocks not in cache • Hardware retrieves information • can quickly match against multiple tags Computer Systems – virtual memory

5. Memory Mountain Computer Systems – virtual memory

6. Page Faults (like “Cache Misses”) What if an object is on disk rather than in memory? • Page table entry indicates virtual address not in memory • OS exception handler invoked to move data from disk into memory • current process suspends, others can resume • OS has full control over placement, etc. Before fault After fault Memory Memory Page Table Page Table Virtual Addresses Physical Addresses Virtual Addresses Physical Addresses CPU CPU Disk Disk Computer Systems – virtual memory

7. VM Address Translation:Hardware vs Software page fault fault handler Processor  Hardware Addr Trans Mechanism Secondary memory Main Memory a a' OS performs this transfer (only if miss) virtual address part of the on-chip memory mgmt unit (MMU) physical address Computer Systems – virtual memory

8. VM Address Translation • Parameters • P = 2p = page size (bytes). • N = 2n = Virtual address limit • M = 2m = Physical address limit n–1 p p–1 0 virtual address virtual page number page offset address translation m–1 p p–1 0 physical address physical page number page offset Page offset bits don’t change as a result of translation Computer Systems – virtual memory

9. Address Translation via Page Table virtual address page table base register n–1 p p–1 0 VPN acts as table index virtual page number (VPN) page offset physical page number (PPN) access valid PTEA = PTE if valid=0 then page not in memory m–1 p p–1 0 physical page number (PPN) page offset physical address Computer Systems – virtual memory

10. miss VA PA Trans- lation Cache Main Memory CPU hit data Integrating VM and Cache • Most Caches “Physically Addressed” • Allows multiple processes to have blocks in cache at same time • Cache doesn’t need to be concerned with protection issues (Access rights checked as part of address translation) • Perform Address Translation Before Cache • But this involves a memory access itself (of the PTE) • Of course, page table entries can also become cached Computer Systems – virtual memory

11. hit miss VA PA TLB Lookup Cache Main Memory CPU miss hit Trans- lation data Speeding up Translation with a dedicated cache • “Translation Lookaside Buffer” (TLB) • Small hardware cache in MMU • Maps virtual page to physical page numbers • Contains complete PTEs for small number of pages Computer Systems – virtual memory

12. What do you know? (ow133)cpuid This system has a Genuine Intel(R) Pentium(R) 4 processor Processor Family: F, Extended Family: 0, Model: 2, Stepping: 7 Pentium 4 core C1 (0.13 micron): core-speed 2 Ghz - 3.06 GHz (bus-speed 400/533 MHz) Instruction TLB: 4K, 2M or 4M pages, fully associative, 128 entries Data TLB: 4K or 4M pages, fully associative, 64 entries 1st-level data cache: 8K-bytes, 4-way set associative, sectored cache, 64-byte line size No 2nd-level cache or, if processor contains a valid 2nd-level cache, no3rd-level cache Trace cache: 12K-uops, 8-way set associative 2nd-level cache: 512K-bytes, 8-way set associative, sectored cache, 64-byte line size Computer Systems – virtual memory

13. VM advance #2: Memory Management • Multiple processes in physical memory. • How do we resolve address conflicts? • what if two processes access something at the same address? memory invisible to user code kernel virtual memory stack %esp Memory mapped region forshared libraries Linux/x86 process memory image the “brk” ptr runtime heap (via malloc) uninitialized data (.bss) initialized data (.data) program text (.text) forbidden 0 Computer Systems – virtual memory

14. Solution: Separate Virt. Addr. Spaces • Each process has its own virtual address space • operating system controls how virtual pages as assigned to physical memory 0 Physical Address Space (DRAM) Address Translation Virtual Address Space for Process 1: 0 VP 1 PP 2 VP 2 ... N-1 (e.g., read/only library code) PP 7 Virtual Address Space for Process 2: 0 VP 1 PP 10 VP 2 ... M-1 N-1 Computer Systems – virtual memory

15. Linux Organizes VM as Collection of “Areas” process virtual memory vm_area_struct task_struct mm_struct vm_end vm_start mm pgd • pgd: • page directory address • vm_prot: • read/write permissions for this area • vm_flags • shared with other processes or private to this process vm_prot vm_flags mmap shared libraries vm_next 0x40000000 vm_end vm_start data vm_prot vm_flags 0x0804a020 text vm_next vm_end 0x08048000 vm_start vm_prot vm_flags 0 vm_next Computer Systems – virtual memory

16. 0: Read? Write? Physical Addr 1: VP 0: VP 0: Yes No PP 9 VP 1: VP 1: Yes Yes PP 4 VP 2: VP 2: No No XXXXXXX • • • • • • • • • Read? Write? Physical Addr Yes Yes PP 6 N-1: Yes No PP 9 No No XXXXXXX • • • • • • • • • VM advance#3: Protection • Page table contains access rights information • hardware enforces this protection (trap into OS if violation occurs) Memory Process i: Process j: Computer Systems – virtual memory

17. vm_end vm_end vm_end vm_start vm_start vm_start r/o r/o r/w vm_next vm_next vm_next Linux Page Fault Handling process virtual memory vm_area_struct • Is the VA legal? • i.e. is it in an area defined by a vm_area_struct? • if not then signal segmentation violation (e.g. (1)) • Is the operation legal? • i.e., can the process read/write this area? • if not then signal protection violation (e.g., (2)) • If OK, handle fault (3) shared libraries 1 read 3 data read 2 text write 0 Computer Systems – virtual memory

18. Assignment • Practice Problem 10.1:Find the largest possible virtual address. • At some point in your lifetime, you find yourself complaining about the cramped 64-bit address space in your computer! Computer Systems – virtual memory