1 / 27

The Tablet PC at Five

The Tablet PC at Five. Chuck Thacker Distinguished Engineer Microsoft Corporation July 20, 2005. Talk outline. Tablet history The Tablet today Tablet futures Limits on computers What Moore actually said. Implications for computers. Other limits What about software? Conclusions.

atalaya
Download Presentation

The Tablet PC at Five

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. The Tablet PC at Five Chuck Thacker Distinguished Engineer Microsoft Corporation July 20, 2005

  2. Talk outline • Tablet history • The Tablet today • Tablet futures • Limits on computers • What Moore actually said. • Implications for computers. • Other limits • What about software? • Conclusions

  3. Prehistory – before 2000 • Lots of earlier attempts – mostly failures. • DEC, Go, Newton, Pen Windows • Technology wasn’t ready • But vertical markets had limited success. • Needed: better UI, better handwriting recognition (without relying on it). • Key: Better digitizer (with hover).

  4. An earlier attempt -- 1983 • TRS 80 Model 100 • Reporters and students loved it • Ran for days on AA cells • Solved most computing needs for its (low aspiration) users.

  5. Another attempt -- 1993 • DEC Lectrice • 5.5 pounds • 1.5 hour battery • Wireless network • $5K LCD panel • VxWorks OS, X11 server optimized for reading

  6. Where we started: Internal MS (1999) • Microsoft proof of concept • Transmeta TM5800 • 256MB DRAM, 20GB HDD • 10.4” Slate • Good points: • Proved viability • Pushed the Power Efficiency Envelope • 5 Hours runtime, 200 Hours standby • Provided a development platform to get MS to Tablet PC launch. • On the Other Hand: • It was so sloooooow

  7. Tatung B12D 12.1” 1.2 GHz Centrino Today’s Market: New Slates MotionComputing LE 1600 LS 800 Sahara i213 12.1”, 1.6GHz Centrino NEC VersaPro, 10.4”, 1.1 GHz Fujitsu 5000 10.4/12.1, Indoor/Outdoor 1.1 GHz ULV Tatung TTAB 10.4”, 1 GHz ULV

  8. Acer C1xx Gateway M275 14.1”, DVD 1.8 GHz Pentium-M C300 C250 SHARP Actius TN10W 12.1”, 1.1 GHz Today’s Market: New Convertibles Toshiba Averatec C3500 AMD 2200+ 12.1”, DVD M200, 12.1” SXGA+ 2 GHz Pentium-M Electrovaya 1.4 GHz Centrino 12.1”, Biometrics Scribbler SC-2200 Fujitsu T4000 HP tc4200 IBM ThinkPad x41 ViewSonic 12.1”, 1 GHz

  9. Today’s Market: New Hybrids & Ruggeds Ruggedized Hybrid Itronix 8.4”, 933 MHz ULV HP Compaq TC1100ULV Celeron or Pentium 10.4”, 1.1 GHz Walkabout Hammerhead 10.4”, 4.5 lbs 933 MHz P-III M Xplore iX104 10.4” 1.1 GHz ULV

  10. Concept Design: New hinge

  11. A Concept Tablet for Kids • Low power • (7W) • 8.4” display • Tethered pen • Rugged

  12. Other Form Factors Vulcan FlipStart OQO Model 1

  13. Today’s Market: Forecasts 2004 Market share 2006 Market share 2008 Market share • Mobile Market Projections (IDC) Consumers, Mobile Professionals CY08 Market: 2.5M, CAGR (04-08): 40% 0% 1% 3% Ultra-Mobile 0 to 1 spindle, 5-8” screen, < 2 lbs. Mobile Professionals, Information Workers CY08 Market: 28.4M, CAGR (04-08): 51.4%, Ultra-Portable 1 or 2 spindle,10-12” screen, 2-4 lbs. 8% 17% 31% Information Workers, Consumers CY08 Market: 51M, CAGR (04-08): 22% Thin & Light 2 spindle, 14-15” screen, 4-7 lbs. 63% 63% 56% Information Workers, Consumers CY08 Market: 8.9M, CAGR (04-08): -11% 30% 19% 10% Transportable 2 & 3 spindle, 14-17” screen, 7-12 lbs. Data source: IDC

  14. Moore’s Law (1967) • Not really a “law”, but an observation, intended to hold for “..the next few years”. • (Nt/A)(t1) = (Nt/A)(t0) * 1.58t1-t0(t in years) • Most exponential curves in the real world turn out to be “S” shaped, but Moore’s observation has held for 35 years.

  15. The Woolly Bear Book of VLSI scaling • Scaling requires lithography and process changes. • Get more and faster transistors in the same area. • Power per transistor goes down, power per unit area goes up (sometimes way up). • Power ≈ CV2f (plus leakage)

  16. How to use Moore’s Law • Lower cost: Same Nt, reduced A (“die shrinks”) used in video consoles. • More complex chips: Larger Nt, same A. • Lower the voltage and increase frequency • Add larger caches to overcome latency • Add architectural features to increase ILP • Superchips (SOC): Increase Nt and A.

  17. Moore’s Law for Memory • Capacity improvement: 1,000,000 X since 1970. • Bandwidth improvement: 100 X. • Latency reduction: only 10-20 X. • Dealing with latency is the largest problem for a computer system designer.

  18. Moore’s Law for Processors • More complex designs • More than one processor on a chip (homogeneous). • More than one processor, with specialized functions, e.g. graphics • Graphics performance is improving much faster than CPU performance.

  19. Thirty years of progress

  20. Possible Future Limits • Physical limits: • “Atoms are too large, and light is too slow” • Today, the problem isn’t making the transistors faster, it’s the time for signals to propagate on the wires (latency again). • Power. Lots of transistors => lots of power. Cooling is hard. • Design complexity: • Designing a billion-transistor chip takes a large team, even with good design tools. • The “junk DNA” problem. • Economics: • Factories are very expensive.

  21. Scaling Limits • Voltage scaling is about over. It’s very hard to operate below 1 volt. • Frequency increases are also difficult. • Intel runs out at 3 – 4 GHz. • Static leakage is also a big problem. • So, we’ll see more transistors in the future, but they won’t be better or faster transistors.

  22. Future processors • We’ll see chips with many processor cores. • Each core will be simpler than today’s superscalar machines. Probably hyperthreaded, to hide latency. • Optimized to increase thread-level parallelism, rather than instruction-level parallelism. • The story about caching is very unclear… • See Intel’s “Platform 2015” white papers.

  23. Other Limits • Not all technologies used in computers follow Moore’s Law • Disks don’t • Displays don’t • Batteries don’t • The bandwidth vs. latency problem. • See D. Patterson, “Latency Lags Bandwidth”, CACM, October 2004

  24. What about software? • For scientific computing and servers, the future seems fine. • There are lots of important problems that are embarrassingly parallel. • For client software, the picture is more bleak.

  25. Many-core challenges for clients • Windows doesn’t use threads well • Exceptions: Kernel, SQL • Competitors don’t do any better • Applications don’t use threads well • Outlook is the poster child • Until recently, inking on Tablet was problematic • Problems: • Writing multi-threaded code is hard • Threading model and primitives are overly complicated • Threads don’t compose • Debugging multi-threaded code is harder • Testing multi-threaded code is a crapshoot • Tool support isn’t very good

  26. Possible paths forward • Better language support for parallelism • Cω, Atomic transactions • Better tools • Analyze liveness and safety statically • Model checking • Dynamic race detection • Better libraries • Better education

  27. Conclusions • Popularity of portable devices, including Tablet PC, is growing • Much of the innovation in the industry is in this area. • Energy-efficiency can open up new markets. • Silicon trends favor the high end • There are lots of challenges and opportunities for new software.

More Related