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Capture and record 1GHz signal (Block Diagram)

Capture and record 1GHz signal (Block Diagram). Data Flow structure. FADC Fast Analog to Digital Convertor. FPGA Choose “Data”. DSP “Dig” more. VMEbus Data Transfer. PC Record & Display. 1GHz Analog Signal. Function Flow structure. Capture (Digitize). Pre-handle (Focus).

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Capture and record 1GHz signal (Block Diagram)

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  1. Capture and record 1GHz signal (Block Diagram) Data Flow structure FADC Fast Analog to Digital Convertor FPGA Choose “Data” DSP “Dig” more VMEbus Data Transfer PC Record & Display 1GHz Analog Signal Function Flow structure Capture (Digitize) Pre-handle (Focus) Handle (Mathematical) Handshake (Transfer) Specification Expand Function Mass Data Real Time Level 1 Cut Pedestal choice MBLT 80MHz Level 2 Cut Width choice Record Time Encode Header, TDC, Trailer

  2. Capture and record 1GHz signal (Realized circuit) Xilinx Spartan-3 XC3S400 500MHz synchronous latch 250MHz synchronous clock XC18V02 National Semiconductor ADC081000 4 ports 8-bits 250MHz MUX 4 ports 8-bits 250MHz FIFO 4 ports 8-bits 250MHz Level 1 Cut Comparator 4 ports 8-bits 250MHz Level 2 Cut Comparator 1GHz Analog Signal 2 ports 8-Bits 500MHz LVDS Data JTAG 1GHz Clock signal 250MHz synchronous clock 8 ports 16-bits 125MHz Encoder Time Counter Trigger 4*32-Bits 125MHz Dual-port RAM 70T3519 TI DSP XC18V01 XilinxCPLD 125MHz XC95288 Interrupter 5V-3.3V Level change Decoder JTAG SN74LS245 SN74LS245 A01-A31 address, LWORD*, IACK*, AM0-AM5

  3. Capture and record 1GHz signal (Power Supply) 3.3V Xilinx Spartan-3 XC3S400 1.2V/2V XC18V02 1.2V/2.5V/3.3V National Semiconductor ADC081000 1GHz Analog Signal JTAG 4*32-Bits 125MHz Dual-port RAM TI DSP 3.3V 5V/3.3V XC18V01 XilinxCPLD 125MHz XC95288 5V/3.3V JTAG SN74LS245 SN74LS245 5V 5V

  4. 1. VMEBus Backplane supply ±5V, ±12V, GND 2. TI-REG104 supply 2.5V,3.3V (Fixed) with input 5V, current 1A (MAX) (Finished) 2.5/3.3V 3. TI-SN105125 supply 1.2V (Fixed) with input 5V, current 150mA (MAX) 1.2V 4. TI-TPS61020 supply 1.8V-5.5V (Adjustable) with input 5V, current 1.5A (MAX) 2V

  5. Capture and record 1GHz signal (Speed Limit) Xilinx Spartan-3 XC3S400 XC18V02 I/O 622MHz Logic: 326MHz National Semiconductor ADC081000 1GHz Analog Signal 800MHz JTAG 1.6GHz 4*32-Bits 125MHz Dual-port RAM TI DSP 166 MHz XC18V01 XilinxCPLD 125MHz XC95288 95 MHz JTAG SN74LS245 SN74LS245 125 MHz 80MHz

  6. CPLD Download XC18V01 XilinxCPLD 125MHz XC95288 Interrupter 5V-3.3V Level change Decoder JTAG SN74LS245 SN74LS245 A01-A31 address, LWORD*, IACK*, AM0-AM5

  7. VMEbus Handshake XC18V01 XilinxCPLD 125MHz XC95288 Interrupter 5V-3.3V Level change Decoder JTAG SN74LS245 SN74LS245 A01-A31 address, LWORD*, IACK*, AM0-AM5

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