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Virtual Memory & Paging

Virtual Memory & Paging. Chapter 4 Thursday, March 22, 2007. Today’s Schedule. Memory Management - Chapter 4 Tracking Free Memory Page Tables Addresses in Paged Memory. Objectives. You will be able to describe: Two methods to track free memory

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Virtual Memory & Paging

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  1. Virtual Memory & Paging Chapter 4 Thursday, March 22, 2007

  2. Today’s Schedule • Memory Management - Chapter 4 • Tracking Free Memory • Page Tables • Addresses in Paged Memory

  3. Objectives You will be able to describe: • Two methods to track free memory • Translation between virtual address and physical address • Structure of Page Table and its entries • How to insure memory access is fast “enough”

  4. Available Memory Management • Part of memory with 5 processes, 3 holes • tick marks show allocation units • shaded regions are free • Corresponding bit map • Same information as a list

  5. Memory Management with Linked Lists Four neighbor combinations for the terminating process X

  6. Paging • Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available • Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8,192 bytes) • Divide logical memory into blocks of same size called pages • Keep track of all free frames • To run a program of size n pages, need to find n free frames and load program • Set up a page table to translate logical to physical addresses • Internal fragmentation

  7. Address Translation Scheme page number page offset • Address generated by CPU is divided into: • Page number (p) – used as an index into a pagetable which contains base address of each page in physical memory • Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit • For given logical address space 2m and page size2n p d m - n n d

  8. Paging Hardware

  9. Paging Model of Logical and Physical Memory

  10. Paging Example 32-byte memory and 4-byte pages

  11. Free Frames After allocation Before allocation

  12. Paging The relation betweenvirtual addressesand physical memory addresses given bypage table

  13. Page Tables Typical page table entry

  14. Page Tables Internal operation of MMU with 16 4 KB pages

  15. Page Tables (3) Typical page table entry

  16. Implementation of Page Table • Page table is kept in main memory • In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. • The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)

  17. Tuesday, March 27 • Assignment #6 Due Monday, March 26 • Continue reading, Chapter 4 – Memory Management through page 220, Sec 2.4.6 LRU Algorithm

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