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Memory Interface

Memory Interface. Rabie A. Ramadan. Agenda. Memory Devices ROM RAM Memory Organization Types of Memory Access Data Transfer Rate Interfacing SRAM to 80x86 Processors. Memory Pyramid. Memory Devices. There are two main types of memory: (1)Read-Only Memory (ROM) Mask-Programmable ROM

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Memory Interface

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  1. Memory Interface Rabie A. Ramadan

  2. Agenda • Memory Devices • ROM • RAM • Memory Organization • Types of Memory Access • Data Transfer Rate • Interfacing SRAM to 80x86 Processors

  3. Memory Pyramid

  4. Memory Devices • There are two main types of memory: (1)Read-Only Memory (ROM) • Mask-Programmable ROM • Field-Programmable ROMs (2) Random Access Memory (RAM) • Static Random Access Memory (SRAM) • Dynamic Random Access Memory (DRAM)

  5. ROM Memory • Permanently stores programs/data for the system. • Its contents do not change even if power is disconnected. • There are two main types of ROM memory: • (1) Mask-Programmable ROM • (2) Field-Programmable ROMs

  6. Mask-Programmable ROMs • It is possible to view a ROM as a device with ninputsand moutputs. • For each of the2ninput combinations, there is one output word of mbits. • A ROM is made up of an address decoder, a programmable memory array, and a set of output buffers. • When a n-bit address is applied to the ROM, one of the 2n row lines will go low. • A diode connected between a row line and a column line will program that output bit low. • The absence of a diode will program a logic 1. • The diode connections are programmed at the factory according to a truth table supplied by the user.

  7. Mask-Programmable ROMs • Example 1: Show the circuit diagram of an 8x4 ROM programmed according to the following truth table:

  8. Field-Programmable ROMs • There are several types of ROMs that can be programmed by the end user: • Programmable ROM (PROM) • Electrically Programmable ROM (EPROM) • Electrically Erasable Programmable ROM (EEPROM) • Flash Memory

  9. Field-Programmable ROMs (PROM) • Uses a low-current fusible link (fuse) in series with each diode in the array. • By applying a current pulse to the desired location, the fuse can be melted (burned) and a logic 1 is permanently programmed. • Once a fuse has been burned, it cannot be altered. • Thus, when a PROM is programmed it cannot be erased. • Therefore PROMs are referred to as one-time programmable.

  10. Field-Programmable ROMs (PROM) • Example 2: Show the circuit diagram of an 8x4 PROM programmed according to the following truth table:

  11. Field-Programmable ROMs (EPROM) • The EPROM (erasable programmable read-only memory) is commonly used when software must be changed often. • An EPROM is programmed in the field on a device called an EPROM programmer. • Also erasable if exposed to high-intensity ultraviolet light.

  12. Field-Programmable ROMs (E2PROM) • EEPROM can be programmed and erased without removing the chip from its socket. • Both byte and bulk erasure modes are possible. • EEPROMs are changed 1 byte at a time, which makes them versatile but slow.

  13. Here is a Question for you

  14. Given the following circuit, what will be the final shape if the following truth table is applied ?

  15. The truth table

  16. Field-Programmable ROMs (Flash) • Flash Memory overcomes this limitation of EEPROM • This device uses in-circuit wiring to erase by applying an electrical field to the entire chip or to predetermined sections of the chip called blocks. • It works much faster than EEPROMs because it writes data in chunks, usually 512 bytes in size, instead of 1 byte at a time.

  17. RAM Memory • RAM stands for random access memory. • This device retain data as long as DC power is applied. • Once the power is turned off all data stored in the RAM will be lost. • The main difference between ROM and RAM is that RAM is written under normal operation, whereas ROM is programmed outside the computer and normally is only read. • There are two main types of RAM: • (1) Static Random Access Memory (SRAM) • (2) Dynamic Random Access Memory (DRAM)

  18. Static RAM (SRAM) • RAM devices retain data as long as DC power is applied (i.e. no special action is required to retain data). • Static RAM (SRAM) uses a flip-flop as the basic storage element. • A typical SRAM memory cell consists of 6 transistors connected as shown in the next figure.

  19. Static RAM (SRAM) Operation • To read the data stored by the SRAM cell: • The Row-select line is made active. • The voltage difference between Column and Column lines is sensed. • A positive voltage indicates a logic 1 is stored. • A negative voltage between these same lines indicates a logic 0 is stored. • To write data into the SRAM cell: • The Row-select lineis made active. • To store a logic 1, the Column line is driven high and the Column line is driven low • To store a logic 0, the process is repeated, but this time the Column line is driven low and Column high.

  20. Dynamic RAM (DRAM) • A DRAM memory cell consists of a single transistor and a capacitor as shown in the next figure. • Thus, DRAM chips are much denser and can hold more data than SRAM in the same size package.

  21. Dynamic RAM (DRAM) • However, capacitors constantly leak electricity, which requires a memory controller to refresh the DRAM several times a second to maintain the data.

  22. Dynamic RAM (DRAM) • The DRAM cell can retain data for only 2 or 4 ms on its integrated capacitor. • After 2 or 4 ms, the content of the DRAM must be completely rewritten (refreshed).

  23. Operation of DRAM • The value stored in the cell is determined by the charge of the capacitor • Charged  logic 1 • Discharged  logic 0

  24. Operation of DRAM • To read the data stored by the DRAM cell: • Pre-charge the bit line to Vcc/2. • Set the word line HIGH. • A sense amplifier is used to determine the logic store in the cell as follows: • If current flows into the cell  the cell is at logic • If current flows out of the cell  the cell is at logic • Cell contents are destroyed by the read! • Hence, the bit value must be written back after reading.

  25. Operation of DRAM • To write data into the DRAM cell: • Set the word line HIGH. • To write logic 1 set the bit line HIGH • To write logic 0 set the bit line LOW • Set the select line LOW. • Note that the stored charge for a 1 will eventually leak off. • Typical devices require each cell to be refreshed once every 2 or 4 ms.

  26. Memory Organization • The organization of a memory chip refers to the way in which its cells are arranged to provide external data access. • For example, a particular chip may have a total of 16 MB of storage. • Externally, however, these 16 Mb may be accessed in several different ways: • (1) 16M x 1 (Le., 16M bits) • (2) 4M x 4 (i.e., 4M nibbles) • (3) 2M x 8 (i.e., 2M bytes) • (4) 1M x 16 (Le. 16M words)

  27. Memory Organization • SRAMs and ROMs are typically arranged as byte-wide (i.e. provide 8-bit external data access). • The organization of a memory chip is important because it determines how many chips will be required in a memory interface.

  28. Memory Organization • Example 3: Using 64K x 8 SRAMs, determine the minimum number of chips required to construct a memory interface to each of the following processors. For each interface, calculate the total memory capacity provided. (a) 8088 (b) 8086 (c) 80486 (d) Pentium

  29. Memory Organization • Example 3: Using 64K x 8 SRAMs, determine the minimum number of chips required to construct a memory interface to each of the following processors. For each interface, calculate the total memory capacity provided.

  30. Types of Memory Access • Depending on the processor, the quantity of data transferred per memory cycle can be: • 1 byte (the 8088) • 2 bytes (the 8086) • 4 bytes (the 386 and 486) • 8 bytes (the Pentium/Pro) D7-D0

  31. Types of Memory Access • Depending on the processor, the quantity of data transferred per memory cycle can be: • 1 byte (the 8088) • 2 bytes (the 8086) • 4 bytes (the 386 and 486) • 8 bytes (the Pentium/Pro)

  32. Types of Memory Access • Depending on the processor, the quantity of data transferred per memory cycle can be: • 1 byte (the 8088) • 2 bytes (the 8086) • 4 bytes (the 386 and 486) • 8 bytes (the Pentium/Pro)

  33. Types of Memory Access • To indicate which bits of the data bus will be involved in the data transfer, the 80x86 processors provide byte enable output pins: • The 8086 (BHE) • The 386 & 486 (BE3-BE0) • The Pentium & Pentium Pro (BE7-BE0)

  34. Types of Memory Access • To indicate which bits of the data bus will be involved in the data transfer, the 80x86 processors provide byte enable output pins: • The 8086 (BHE) • The 386 & 486 (BE3-BE0) • The Pentium & Pentium Pro (BE7-BE0)

  35. Types of Memory Access • Using these byte enable signals, the 80x86 processors can indicate that: • (1) A single byte is to be transferred (only one byte enable signal active). • (2) A word is to be transferred (two byte enable signals active). • (3) A double-word is to be transferred (four byte enable signals active). • (4) A quad-word is to be transferred (all eight byte enable signals active). • Note that, when a memory transfer occurs, consecutive memory locations must be accessed,

  36. Types of Memory Access • Example 4: Assume a Pentium processor executes the following instructions. Indicate the logic state of the BE7-BE0 byte enables for each associated memory access. (a) MOV AL,[0000] (b) MOV AX,[0000] (c) MOV EAX,[0000]

  37. Types of Memory Access • Example 4: Assume a Pentium processor executes the following instructions. Indicate the logic state of the BE7-BE0 byte enables for each associated memory access.

  38. Types of Memory Access (Alignment) • Data is said to be aligned if all of the bytes to be accessed are located within the same n-byte boundary where n is the maximum number of bytes that can be transferred per memory cycle. • For example the 386 and 486 processors can access 1 byte, 2 bytes, and 4 bytes using BE3-BE0. • Thus, data is said to be aligned if all of the bytes to be accessed are located within the same 4-byte boundary.

  39. Types of Memory Access (Alignment) • Four such address boundaries are possible for 386 and 486 processors as shown in the next figure. • Data items that span across two of these boundaries are said to be misaligned and will require that two bus cycles be performed.

  40. Types of Memory Access (Alignment) • Example 5: Assume a 486 processor executes the instruction MOV EAX, [00005]. Which byte enable signals will be active? How many bus cycles will be required?

  41. Types of Memory Access (Alignment) • Example 5: Assume a 486 processor executes the instruction MOV EAX, [00005]. Which byte enable signals will be active? How many bus cycles will be required? * The double-word (four bytes) at address 0005-0008 is to be accessed. * Two bus cycles will be required: 1st bus cycle will be run with BE1-BE3 active and transfer the three bytes at address 0005-0007. 2nd bus cycle will be run with only BE0 active. This will transfer the byte at address 0008.

  42. Data Transfer Rate • Data Rate is the quantity of data (measured in bytes) that a processor can transfer in one second. • It can be computed as:

  43. Data Transfer Rate • The time for one bus cycle can be written as: • Where n represents the number of system clock pulses per bus cycle, • Tclock is the period of the external bus clock, and • f is the frequency of the bus clock. • Substituting into the Equation in the previous slide, we obtain:

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