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MSD Group induction

MSD Group induction. Meeting on 19 October 2007. What is MSD Group. Academic Members (7): A.Bystrov, E.G. Chester, J.N. Coleman, D.J.Kinniment, A.M. Koelmans, G.Russell, A.Yakovlev Research Associates (6): F.P. Burns, F. Xia, D. Sokolov, D. Shang, J.Murphy, H. Ramakrishnan

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MSD Group induction

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  1. MSD Group induction Meeting on 19 October 2007

  2. What is MSD Group • Academic Members (7): • A.Bystrov, E.G. Chester, J.N. Coleman, D.J.Kinniment, A.M. Koelmans, G.Russell, A.Yakovlev • Research Associates (6): • F.P. Burns, F. Xia, D. Sokolov, D. Shang, J.Murphy, H. Ramakrishnan • 25+ postgraduate research students • Links to other groups in the school (NanoMicroElectronics, Comms&SP, PowerDrivesMachines) and CS school (Concurrency and Security Groups)

  3. Agenda • (1) Group's research directions and vision for the future • (2) Research projects and grants • (3) Further grant applications • (4) Miscelleneous external collaborations • (5) Industrial links • (6) Work on research papers • (7) Conferences and workshops (inc. ASYNC'08 and NOCS'08) • (8) Training Courses (Europractice) • (9) CAD tools and training (MSD CAD Users Group) • (10) Team work in the group: Ras+PhDs, later years PhDs + first year PhDs, involvement of MSc's and undegraduates • (11) Career prospects

  4. Research directions and vision for future • 1. Microelectronic Systems Design and Test as a whole (incl. Advanced Processor Design) • 2. Asynchronous (Self-Timed) and Mixed Synchronous-Asynchronous (GALS) systems • 3. Design Automation for Asynchronous Systems (System and logic synthesis and verification) • 4. Off-line and On-line Testing (Built-in, On-line, Concurrent Error Detection) • 5. On-chip Time Measurement for Deep-Submicron • 6. Synchronisation, Synchroniser Design (metastability analysis and characterisation) • 7. Hardware design for security (balancing, randomisation, differential power analysis and fault analysis, countermeasures) • 8. Process, Device and Circuit Variability Modelling and Characterisation

  5. Current Research Grants Current EPSRC portfolio: • (1) "Synchronizer Reliability in the Next Generation of SoC" £219,200 (2005-8), collab. with Intel Strategic Research Labs • (2) "Next Generation of Interconnection Technology for Multiprocessor SoC" £ 293,570 (2005-8), collab. with Univ. So’ton and MBDA UK • (3) "Secure circuit design" £ 526,124 (2004-7), collab. with Atmel Smart Card ICs • Follow-up, “Secure Design Flow”, has started Oct 2007 (end 2010) • (4) “Self-timed Event Processor" £ 371,922 (2007-10), collab. With MBDA UK • (5) “Self-timed Datapath synthesis” £311,649 (2006-2009), Collab. With Uni. Manchester and Silistix UK • (6) “EDA tools for strained Si CMOS cell libraries with variability models” £159,357 (2007-2009)

  6. Areas for further grant applications • Next Generation Energy-Harvesting Electronic Systems – joint research proposal with So’ton, Imperial and Bristol, involving research on: • Novel micro-generator and transducer electronics • EH-aware computational electronics • New CAD tool support for EH electronic systems • Adaptive and Reconfigurable Networks on Chips – possible joint proposal with Imperial College • To address issues of optimal adaptation to parametric instabilities for future Systems on Chip • Elastic Logic Synthesis – joint proposal with So’ton • To address issues of low (dynamic and static) power consumption, and interconnect variations in an automatic flow using concepts of GALS and Elastic data processing

  7. Key External Collaborations • Within UK: • Microelectronic Design Community: Manchester, So’ton, Cambridge, Imperial, Leicester • Industrial: Atmel, Silistix, MBDA • International: • Async Design Community: Barcelona, Turin, Boston • Industrial: Intel, Sun, Elastix

  8. Industrial Links and examples • Different levels of collaboration • Methodological, review meetings etc (MBDA, Silistix) • Technology transfer, examples, case studies, experiments (Atmel, Intel) • Help with fabrication and tools (Sun) • Consultancy and R&D projects (Elastix) • General interest, Letters of Support (all of the above, plus Cadence, Sharp) • Student placement (Sharp LE)

  9. Work on research papers • Research Papers is the main output from our research activity. Important factors: Research Assessment Exercise, Group track record, Individual CVs • Typical publication line: Tech Report, Conference, Journal • Typical line for PhDs: Year 1 – TRs, Year 2- Conf, Year 3- Journal • Conf papers are typically deadline driven • Key Journals to target: IEEE Transactions on CAD, VLSI, Computers, CAS, IEEE Journal of SSC, IET Proceedings CDT etc.

  10. Conferences and workshops • Key conferences: ASYNC, NOCS, DATE, DAC, ICCAD, PATMOS, ICCD, IOLTS, CHES • Staff are members of TPCs of many of those • Publications • Training and Knowledge transfer • Networking with other people and peers • But … Travel budget is limited: • Research grants mostly • Some small support from school, Hence it is important to gain max impact from conf. attendance!

  11. Training Courses • Europractice courses: • RAL • IMEC • Tutorials within conferences: • DATE • DAC

  12. For example:

  13. CAD Tools and Training • MSD CAD Users Group (Enzo and Robin coordinators) • Wiki Materials • Lectures (UG and MSc) and Coursework • Embedded Systems • Digital Electronics • EDA Tools for VLSI • Async and Low Power systems

  14. Team Work in the Group • RAs+PhDs (e.g. research grants) • Later years PhDs + first year PhDs (mini projects) • Master-Apprentice situation: • Idea, problem formulation level (Academic, RA) • Method level (RA, PhD senior) • Implementation level (PhD) • Involvement of MSc's and undergraduates • Individual and group projects, study projects

  15. Career Prospects • …. • E.g. JOB VACANCY at PII PIPELINE SOLUTIONS LTD: ELECTRONICS DESIGN ENGINEER The World’s economies rely upon the transmission of oil and gas through millions of kilometres of high pressure steel pipelines. Protecting these “life-blood” assets is our business. This requires the most sophisticated NDT technologies applied to robotic inspection systems. These systems travel autonomously through the pipelines sampling thousands of sensors every few millimetres, over distances of up to 1000km. Processing and capturing all this data requires innovative engineering solutions, especially on the electronics design front. PII is the World leader in the development of these inspection systems, known as intelligent pigs. We now have a vacancy for an Electronics Design Engineer within the Engineering Department at Cramlington, Northumberland.

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