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Sequential circuit

Sequential circuit. Digital electronics is classified into combinational logic and sequential logic. In combinational circuit outpus depends only on present inputs. In sequential circuit, output depends upon both present and previous inputs/outputs.

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Sequential circuit

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  1. Sequential circuit • Digital electronics is classified into combinational logic and sequential logic. • In combinational circuit outpus depends only on present inputs. • In sequential circuit, output depends upon both present and previous inputs/outputs. • because of this sequential ckthae memory to store the previous inputs. • Hence sequential ckt always contains a memory element or a feedback from output to input or boyh.

  2. Basic element of sequential circuitLATCH • RS Latch: IT STORE 1-BIT.

  3. The waveform below shows the operation of NOR gates based RS Latch.

  4. Clocked S - R Latch

  5. Clocked S - R Latch (continued)

  6. S-R flip flop

  7. T-flip flop

  8. J-K Flip flop

  9. Flip-Flop Problem • The change in the flip-flop output is delayed by the pulse width which makes the circuit slower or • S and/or R are permitted to change while C = 1 • Suppose Q = 0 and S goes to 1 and then back to 0 with R remaining at 0 • The master latch sets to 1 • A 1 is transferred to the slave • Suppose Q = 0 and S goes to 1 and back to 0 and R goes to 1 and back to 0 • The master latch sets and then resets • A 0 is transferred to the slave • This behavior is called 1s catching

  10. Flip-Flop Solution • Use edge-triggering instead of master-slave • An edge-triggered flip-flop ignores the pulse while it is at a constant level and triggers only during a transition of the clock signal • Edge-triggered flip-flops can be built directly at the electronic circuit level, or • A master-slave D flip-flop which also exhibits edge-triggered behavior can be used.

  11. D D S Q Q Q C C C Q R Q Q Edge-Triggered D Flip-Flop • The edge-triggered D flip-flop is thesame as the master-slave D flip-flop • It can be formed by: • Replacing the first clocked S-R latch with a clocked D latch or • Adding a D input and inverter to a master-slave S-R flip-flop • The delay of the S-R master-slave flip-flop can be avoided since the 1s-catching behavior is not present with D replacing S and R inputs • The change of the D flip-flop output is associated with the negative edge at the end of the pulse • It is called a negative-edge triggered flip-flop

  12. D D S Q Q Q C C C Q R Q Q Positive-Edge Triggered D Flip-Flop • Formed byadding inverterto clock input • Q changes to the value on D applied at the positive clock edge within timing constraints to be specified • Our choice as the standard flip-flop for most sequential circuits

  13. S S D D R R C C SR D with 1 Control SR (a) Latches S S D D C C R R C C Triggered D Triggered SR Triggered SR (b) Master-Slave Flip-Flops D D C C Triggered D Triggered D (c) Edge-Triggered Flip-Flops Standard Symbols for Storage Elements • Master-Slave:Postponed outputindicators • Edge-Triggered:Dynamicindicator D with 0 Control Triggered D

  14. Registers

  15. 4-bit Register

  16. Shift Register

  17. Shift Register

  18. Ripple Counter

  19. Synchronous Counter • All flip-flops have a common clock & are synchronized • Flip-flop in lowest-order position is complemented with every pulse. • Lowest flip-flop has J=K=1 • Chain of AND gates generates the required logic for the J & K inputs in each stage • The counter can be extended to any number of stages, with each stage having an additional flip-flop and an AND gate that gives an output of 1 if all previous flip-flop outputs are 1s

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