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CMOS SEQUENTIAL CIRCUIT DESIGN

CMOS SEQUENTIAL CIRCUIT DESIGN. Integrated Circuits Spring 2001 Dept. of ECE University of Seoul. Combinational vs. Sequential Logic.  Combinational Logic OUT(t)  IN(t).  Sequential Logic OUT(t)  IN(t)  IN(t-kT)  OUT(t-kT).  Positive Feedback  Charge on Cap.

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CMOS SEQUENTIAL CIRCUIT DESIGN

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  1. CMOS SEQUENTIAL CIRCUIT DESIGN Integrated Circuits Spring 2001 Dept. of ECE University of Seoul

  2. Combinational vs. Sequential Logic •  Combinational Logic • OUT(t)  IN(t)  Sequential Logic OUT(t)  IN(t)  IN(t-kT)  OUT(t-kT)  Positive Feedback  Charge on Cap.

  3. Sequential Logic w/ Positive Feedback •  Two Inverters in Positive Feedback •  STATIC

  4. Bi-stability •  Transition Region  Stable Regions •  Slope (Gain) >1

  5. R S Q Q S Q 0 Q 0 Q S Q 0 0 1 1 Q R 0 1 0 1 Q R 1 0 1 0 R S Q Q S Q S Q 1 Q 1 Q Q R 0 1 1 0 Q R 1 0 0 1 0 1 0 1 SR Latch •  NOR-Based  NAND-Based

  6. L H H Q L L H ? Q H H H L H HL L L H JK Flip-Flop f=H

  7. T-FF & D-FF

  8. Race Problem of Latch

  9. H L L L H H L H Master/Slave Flip-Flop • master slave  One-Catching  Level-Sensitive Input Data Valid @ f=High

  10. Edge-Triggered Operation 1

  11. Edge-Triggered Operation 2

  12. Flip-Flop Timing Constraints •  Setup Time tsetup Hold Time thold •  Propagation Delay tpFF

  13. Flip-Flop Timing Example • T > tpFF + tp,comb + tsetup f Y Q FF’s LOGIC tp,comb

  14. CMOS Latches

  15. Pseudo-Static D-Latch  f=High (Data I/O)  f=Low (Data Store)

  16. M/S D-FF (pseudo-Static) •  f=High  New Data In & Previous Data Store  f=Low  New Data Out & New Data Store

  17. M/S D-FF (pseudo-Static) Problem

  18. M/S D-FF Problem Solution Non-Overlapping 2-Phase Clocks

  19. Dynamic M/S D-FF

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