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System components

System components. Timing diagrams. Memory. Busses and interconnect. Timing diagrams. A timing diagram shows a trace through the operation of a system. Generally used for asynchronous machines with timing constraints. enq. ack. Timing diagram syntax. Constant value: Stable: Changing:

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System components

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  1. System components • Timing diagrams. • Memory. • Busses and interconnect. Overheads for Computers as Components

  2. Timing diagrams • A timing diagram shows a trace through the operation of a system. • Generally used for asynchronous machines with timing constraints. enq ack Overheads for Computers as Components

  3. Timing diagram syntax • Constant value: • Stable: • Changing: • Unknown: 1 0 Overheads for Computers as Components

  4. Timing constraints • Minimum time between two events: enq 20 ns ack Overheads for Computers as Components

  5. Origin of timing constraints • Control signals are passed on the bus: D Q 20 ns c a Overheads for Computers as Components

  6. Memory device organization Memory array n r c Overheads for Computers as Components

  7. Memory parameters • Size. • Address width. • Aspect ratio. • Data width. Overheads for Computers as Components

  8. Types of memory • ROM: • Mask-programmable. • Flash programmable. • RAM: • DRAM. • SRAM. Overheads for Computers as Components

  9. SRAM vs. DRAM • SRAM: • Faster. • Easier to integrate with logic. • Higher power consumption. • DRAM: • Denser. • Must be refreshed. Overheads for Computers as Components

  10. Typical generic SRAM SRAM CE’ R/W’ Adrs Data Overheads for Computers as Components

  11. Generic SRAM timing CE’ R/W’ Adrs From SRAM From CPU Data read write time Overheads for Computers as Components

  12. Generic DRAM device CE’ DRAM R/W’ RAS’ CAS’ Adrs Data Overheads for Computers as Components

  13. Generic DRAM timing CE’ R/W’ RAS’ CAS’ row adrs col adrs Adrs Data data time Overheads for Computers as Components

  14. Page mode access CE’ R/W’ RAS’ CAS’ row adrs col adrs col adrs col adrs Adrs Data data data data time Overheads for Computers as Components

  15. RAM refresh • Value decays in approx. 1 ms. • Refresh value by reading it. • Can’t access memory during refresh. • CAS-before-RAS refresh. • Hidden refresh. Overheads for Computers as Components

  16. Other types of memory • Extended data out (EDO): improved page mode access. • Synchronous DRAM: clocked access for pipelining. • Rambus: highly pipelined DRAM. Overheads for Computers as Components

  17. Flash issues • Flash is programmed at system voltages. • Erasure time is long. • Must be erased in blocks. Overheads for Computers as Components

  18. Generic bus structure m • Address: • Data: • Control: n c Overheads for Computers as Components

  19. Electrical bus design • Bus signals are usually tri-stated. • Address and data lines may be multiplexed. • Every device on the bus must be able to drive the maximum bus load: • Bus wires. • Other bus devices. • Bus may include clock signal. • Timing is relative to clock. Overheads for Computers as Components

  20. data 3 1 2 Four-cycle handshake enq 4 ack Overheads for Computers as Components

  21. Busses as communicating machines enq = 1 ack = 0 0 0 ack enq 1 1 enq = 0 ack = 1 1 1 ack enq 0 0 M1 M2 Overheads for Computers as Components

  22. When should you handshake? • When response time cannot be guaranteed in advance: • Data-dependent delay. • Component variations. Overheads for Computers as Components

  23. Fixed-delay memory access read = 1 adrs = A R/W W R/W data mem[adrs] = data R adrs data = mem[adrs] reg = data memory CPU Overheads for Computers as Components

  24. Variable-delay memory access read = 1 adrs = A R/W done = 0 mem[adrs] = data done = 1 data W R/W R n adrs done data = mem[adrs] done = 1 y done memory reg = data CPU Overheads for Computers as Components

  25. Typical bus access clock R/W’ Address enable adrs Data Ready’ data write read time Overheads for Computers as Components

  26. Bus mastership • Bus master controls operations on the bus. • CPU is default bus master. • Other devices may request bus mastership. • Separate set of handshaking lines. • CPU can’t use bus when it is not master. Overheads for Computers as Components

  27. Direct memory access (DMA) • DMA provides parallelism on bus by controlling transfers without CPU. memory I/O CPU DMA Overheads for Computers as Components

  28. DMA operation • CPU sets up DMA transfer: • Start address. • Length. • Transfer block length. • Style of transfer. • DMA controller performs transfer, signals when done: • Cycle-stealing. • Priority. Overheads for Computers as Components

  29. ARM busses • AMBA: • Open standard. • Many external devices. • Two varieties: • AMBA High-Performance Bus (AHB). • AMBA Peripherals Bus (APB). I/O memory CPU bridge AHB APB Overheads for Computers as Components

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